Toshiba H1 Series Data Book page 25

3.3.1 Block diagram of system clock
SYSCR0<XTEN >
XT1
Low frequency
Oscillator circuit
XT2
X1
High frequency
Oscillator circuit
f
X2
OSCH
X1USB
f
SYS
f
io
φT0TMR
φT0
f
USB
SYSCR0<WUEF>
SYSCR2<WUPTM1:0>
Warming up timer
(High/Low frequency oscillator circuit)
Lock up timer
(PLL)
PLLCR1<PLLON>,
PLLCR0<LUPFG>
fs
f
PLL
Clock Doubler0
(PLL0)
÷2
× (12 or16)
PLLCR0<FCSEL>
Clock Doubler1
(PLL1)× 24
TMRA0:7,TMRB0:1
Prescaler
SIO0
Prescaler
SBI
Prescaler
RTC
fs
MLD/ALM
ADC
Figure 3.3.2 Block Diagram of System clock
92CZ26A-22
fc
fc/2
fc/4
fc/8
fc/16
÷2 ÷4 ÷8 ÷16
SYSCR1<GEAR2:0>
Clock gear
SYSCR0<USBCLK1:0>
f
PLLUSB
÷5
CPU
RAM
Interrupt
Controller
I/O ports
SDRAMC
DMAC
MAC
USB
TMP92CZ26A
÷4 φT0
φT0TMR
÷2
÷2
÷8
SYSCR0<PRCK>
fs
f
SYS
÷2
f
IO
f
USB
LCDC
Memory
Controller
NAND-Flash
Controller
f
OSCH4
2
I S
TSI
SPIC