Toshiba H1 Series Data Book page 352

SBISR Bit symbol
(1243H)
Read/Write
After reset
Prohibit
Function Master/
Read-modif
Slave status
y-write
monitor
0:Slave
1:Master
Note1: Writing in this register functions as SBICR2.
Note2: The initialdata SBISR<PIN> is "1" if SBI operation is enable (SBICR0<SBIEN>="1"). If SBI operation is disable
(SBICR0<SBIEN>="0"), the initialdata of SBISR<PIN> is "0".
Serial Bus Interface Status Register
7 6 5
MST TRX BB
0 0 0
2
Transmitter/ I C bus
Receiver status
status monitor
monitor 0:Free
1:Busy
0:Receiver
1:Tranmitter
Figure 3.15.6 Registers for the I
92CZ26A-349
4 3
PIN AL
R
1 0
INTSBI Arbitration Slave
interrupt lost address
request detection match
monitor monitor detection
0: −
0: Interrupt monitor
requested 1: Detected
0: Undetected
1: Interrupt 1: Detected
canceled
Last received bit monitor
0
1
GENERAL CALL detection monitor
0
1
Slave address match detection monitor
0
1
Arbitration lost detection monitor
0
1
2
C bus mode
TMP92CZ26A
2 1 0
AAS AD0 LRB
0 0 0
GENERAL Last
CALL received bit
detection monitor
monitor 0: 0
1: 1
0: Undetected
1: Detected
Last received bit was 0
Last received bit was 1
Undetected
GENERAL CALL detected
Slave address don't match or Undetected
Slave address match or GENERAL
CALL detected
−
Arbitration lost