Toshiba H1 Series Data Book page 422

Below is control flow in UDC watch from application.
Start up
Setting each EP mode
in Set_Config (Interface)
Enumeration
Control RD transfer
Get_Vendor_Request
transaction
EP0 bit = 1
EP0 bit = 0
Check
DATASET
register
Total ≥ payload
WR number of payload
to EP0_FIFO register
Total = Total − payload
Receive
except
INT_STATUS
Abnormal
finish
Normal
finish
Receive
INT_STAS
Figure 3.16.6 Control Flow in UDC Watch from Application
Note 1: There is not special case in this flow such as overlap receive SETUP packet.
Please refer to chaptor 4.5.2.3.
Note 2: This flow shows various request. However, transaction can be divided every each interrupt.
IDLE
Judge request RD
Access to SetupReceived register
Transmit
judgement
Total_Length
Total < payload
WR number of rest data
to EP0_FIFO
Total = 0
Status finish
transacrion in UDC
92CZ26A-419
Standard request
Printerclass request
Control WR transfer
Set_Vendor_Request
EP0 bit = 0
EP0 bit = 1
Check
DATASET
register
Total > payload
RD number of payload RD number of rest data
from EP0_FIFO register from EP0_FIFO
Total = Total − payload
Total = 0
WR "0" only EP0 bit0 of
EOP register
TMP92CZ26A
transaction
Receive
judgement
Total_Length
Total ≤ payload Total = 0
Not
transaction
Total = 0