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Toshiba TMP96C141AF Manual

Cmos 16-bit microcontroller
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TOSHIBA
TLCS-900 Series
CMOS 16-bit Microcontroller
TMP96C141AF
1. Outline and Device Characteristics
The TMP96C141AF is high-speed advanced 16-bit microcon-
troller developed for controlling medium to large-scale equip-
ment.
The TMP96C141AF is housed in an 80-pin flat package.
Device characteristics are as follows:
(1) Original 16-bit CPU
• TLCS-90 instruction mnemonic upward compatible.
• 16M-byte linear address space
• General-purpose registers and register bank system
• 16-bit multiplication/division and bit transfer/arithmetic
instructions
• High-speed micro DMA
- 4 channels (1.6 µ s/2 bytes @ 20MHz)
(2) Minimum instruction execution time
- 200ns @ 20MHz
(3) Internal RAM: 1K byte
The information contained here is subject to change without notice.
The information contained herein is presented only as guide for the applications of our products. No responsibility is assumed by TOSHIBA for any infringements of patents or other rights of the third parties
which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of TOSHIBA or others. These TOSHIBA products are intended for usage in general electronic
equipments (office equipment, communication equipment, measuring equipment, domestic electrification, etc.) Please make sure that you consult with us before you use these TOSHIBA products in equip-
ments which require high quality and/or reliability, and in equipments which could have major impact to the welfare of human life (atomic energy control, spaceship, traffic signal, combustion control, all types
of safety devices, etc.). TOSHIBA cannot accept liability to any damage which may occur in case these TOSHIBA products were used in the mentioned equipments without prior consultation with TOSHIBA.
TOSHIBA CORPORATION
Internal ROM: None
(4) External memory expansion
• Can be expanded up to 16M bytes (for both programs and
data).
• Can mix 8- and 16-bit external data buses.
...
Dynamic data bus sizing
(5) 8-bit timers: 2 channels
(6) 8-bit PWM timers: 2 channels
(7) 16-bit timers: 2 channels
(8) Pattern generators: 4 bits, 2 channels
(9) Serial interface: 2 channels
(10) 10-bit A/D converter: 4 channels
(11) Watchdog timer
(12) Chip select/wait controller: 3 blocks
(13) Interrupt functions
... ...
• 3 CPU interrupts
SWI instruction, privileged violation,
and Illegal instruction
• 14 internal interrupts
• 6 external interrupts
(14) I/O ports
(15) Standby function : 3 halt modes (RUN, IDLE, STOP)
TMP96C141AF
7-level priority can be set.
1

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Summary of Contents for Toshiba TMP96C141AF

  • Page 1 The information contained herein is presented only as guide for the applications of our products. No responsibility is assumed by TOSHIBA for any infringements of patents or other rights of the third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of TOSHIBA or others. These TOSHIBA products are intended for usage in general electronic equipments (office equipment, communication equipment, measuring equipment, domestic electrification, etc.) Please make sure that you consult with us before you use these TOSHIBA products in equip-...
  • Page 2 TMP96C141AF Figure 1. TMP96C141AF Block Diagram TOSHIBA CORPORATION...
  • Page 3 TMP96C141AF 2. Pin Assignment and Functions 2.1 Pin Assignment The assignment of input/output pins for TMP96C141AF, their Figure 2.1 shows pin assignment of TMP96C141AF. name and outline functions are described below. Figure 2.1 Pin Assignment (80-pin QFP) TOSHIBA CORPORATION...
  • Page 4 TMP96C141AF 2.2 Pin Names and Functions The names of input/output pins and their functions are described below. Table 2.2. Pin Names and Functions Number Pin Name Functions of Pins P00 ~ P07 Port 0: I/O port that allows I/O to be selected on a bit basis...
  • Page 5 TMP96C141AF Number Pin Name Functions of Pins Port 41: I/O port (with pull-up resistor) Output Chip select 1: Outputs 0 if address is within specified address area. CAS1 Output Column address strobe 1: Outputs CAS strobe for DRAM if address is within specified address area.
  • Page 6 Non-maskable interrupt request pin: Interrupt request pin with falling edge. Input Can also be operated at rising edge by program. Clock output: Outputs X1 ÷ 4 clock. Pulled-up during reset. Output External access: 0 should be inputted with TMP96C141AF Input 1, with TMP96CM40F/TMP96PM40F. Output Address latch enable...
  • Page 7 3.1.1 Reset • Sets port pins (including pins also used as built-in I/Os) to To reset the TMP96C141AF, the RESET input must be kept at general-purpose input/output port mode (sets I/O ports to 0 for at least 10 system clocks (10 states: 1 µ s with a 20MHz input ports).
  • Page 8 TMP96C141AF 3.2 Memory Map Figure 3.2 is a memory map of the TMP96C141AF. Figure 3.2 Memory Map TOSHIBA CORPORATION...
  • Page 9 Non-maskable inter- mask flip-flop (IFF2 to 0) and the built-in interrupt controller. rupts have a fixed priority of 7. The TMP96C141AF have altogether the following 23 When an interrupt is generated, the interrupt controller interrupt sources: …...
  • Page 10 TMP96C141AF Figure 3.3 (1) Interrupt Processing Flowchart TOSHIBA CORPORATION...
  • Page 11 TMP96C141AF 3.3.1 General-Purpose Interrupt Processing When accepting an interrupt, the CPU operates as follows: Bus Width of Stack Interrupt Processing State Number Area MAX mode Min mode (1) The CPU reads the interrupt vector from the interrupt 8 bit controller. When more than one interrupt with the same...
  • Page 12 TMP96C141AF Table 3.3 (1) TMP96C141AF Interrupt Table High-Speed Vector Value Default Priority Type Interrupt Source Start Address Micro DMA “V” Start Vector Reset , or SW10 instruction 0 0 0 0 H 8 0 0 0 H – INTPREV: Privileged violation, or SWI1...
  • Page 13 TMP96C141AF (1) High-Speed Micro DMA Operation mode which is set by the CS/WAIT controller) can be accessed by high-speed micro DMA processing. High-speed micro DMA operation starts when the accepted There are two data transfer modes: one-byte mode and interrupt vector value matches the micro DMA start vector one-word mode.
  • Page 14 TMP96C141AF The following timing chart is a high-speed µ DMA cycle of cept the Read-only mode is same as this) the Transfer Address Increment mode (the other mode exe- (Condition: MIN mode, 16bit Bus width for 16M Byte, 0 wait) (2) Register Configuration (CPU Control Register)
  • Page 15 TMP96C141AF (3) Transfer Mode Register Details This condition is 16-bit bus width and 0 wait of source/destination address space. n: corresponds to high-speed µ DMA channels 0 - 3. Note: DMADn +/DMASn + : Post-increment (Increments register value after transfer.) DMADn -/DMASn - : Post-decrement (Decrement register value after transfer.)
  • Page 16 TMP96C141AF <Usage of read only mode (DRAM refresh)> ity setting register, and a register for storing the high-speed micro DMA start vector. The interrupt request flip-flop is used When the hardware configuration is as follows: to latch interrupt requests from peripheral devices. The flip-flop...
  • Page 17 TMP96C141AF Figure 3.3.3 (1) Block Diagram of Interrupt Controller TOSHIBA CORPORATION...
  • Page 18 TMP96C141AF (1) Interrupt Priority Setting Register TOSHIBA CORPORATION...
  • Page 19 TMP96C141AF (2) External Interrupt Control TOSHIBA CORPORATION...
  • Page 20 TMP96C141AF (3) High-Speed Micro DMA Start Vector tor). When both match, the interrupt is processed in micro DMA mode for the channel whose value matched. When the CPU reads the interrupt vector after accepting an inter- If the interrupt vector matches more than one chan-...
  • Page 21 3.4 Standby Function other built-in circuits halt. Power consump- tion is reduced to 1/10 or less than that dur- When the HALT instruction is executed, the TMP96C141AF ing normal operation. enters RUN, IDLE, or STOP mode depending on the contents of the HALT mode setting register.
  • Page 22 TMP96C141AF Table 3. 4 (1) Pin States in STOP Mode 96C141AF 96CM40/96PM40 Pin Name DRVE = 0 DRVE = 1 DRVE = 0 DRVE = 1 Input mode/AD0 ~ 7 – – – – Output mode – Output Input mode/AD8 ~ 15 –...
  • Page 23 The TMP96CM40F/TMP96PM40F has 65 bits for I/O ports. and internal I/Os as well as general-purpose I/O port func- The TMP96C141AF, TMP96C041AF has 47 bits for I/O ports tions. Table 3.5 lists the function of each port pin. because Port0, Port1, P30, and P31 are dedicated pins for ↑...
  • Page 24 To set port pins for built-in functions, a program is Bus release function required. The TMP96C141AF has the internal pull-up and pull- Since the TMP96C141AF has an external ROM, some down resistors to fix the bus control signals at bus release.
  • Page 25 Port 1 also functions as an address data bus (AD8 to 15) or an cleared to 0. address bus (A8 to 15). With the TMP96C141AF/TMP96C041AF, which comes With the TMP96C141AF/TMP96C041AF, which comes with an external ROM, Port 0 always functions as an address...
  • Page 26 TMP96C141AF Port 0 Register Figure 3.5 (3). Registers for Ports 0 and 1 TOSHIBA CORPORATION...
  • Page 27 TMP96C141AF 3.5.3 Port 2 (P20 - P27) input mode and connects a pull-down resistor. To disconnect the pull-down resistor, write 1 in the output latch. Port 2 is an 8-bit general-purpose I/O port. I/O can be set on In addition to functioning as a general-purpose I/O port,...
  • Page 28 TMP96C141AF Figure 3.5 (5). Registers for Port 2 TOSHIBA CORPORATION...
  • Page 29 TMP96C141AF 3.5.4 Port 3 (P30 - P37) With the TMP96C141AF, when P30 pin is defined as RD signal output mode (<P30F> = 1), clearing the output latch Port 3 is an 8-bit general-purpose I/O port. register <P30> to 0 outputs the RD strobe (used for the...
  • Page 30 TMP96C141AF Figure 3.5 (6). Port 3 (P30, P31, P32, P35, P36, P37) TOSHIBA CORPORATION...
  • Page 31 TMP96C141AF Figure 3.5 (7). Port 3 (P33, P34) TOSHIBA CORPORATION...
  • Page 32 TMP96C141AF Port 3 Register Note: When P33/WAIT pin is used as a WAIT pin, set P#CR <P33C> to “0” and Chip Select/Wait control register. Figure 3.5 (8). Registers for Port 3 TOSHIBA CORPORATION...
  • Page 33 TMP96C141AF 3.5.5 Port 4 (P40 - P42) In addition to functioning as a general-purpose I/O port, Port 4 also functions as a chip select output signal (CS0 to Port 4 is a 3-bit general-purpose I/O port. I/O can be set on a CS2 or CAS0 to CAS2).
  • Page 34 TMP96C141AF Figure 3.5 (9). Port 4 TOSHIBA CORPORATION...
  • Page 35 TMP96C141AF Port 4 Register Note: To output chip select signal (CS0/CAS0 to CS2/CAS2), set the corresponding bits of the control register P4CR and the function register to P4FC. The BOCS, B1CS, and B2CS registers of the chip select/wait controller are used to select the CS/CAS function.
  • Page 36 TMP96C141AF 3.5.6 Port 5 (P50 - P53) Port 5 is a 4-bit input port, also used as an analog input pin. Figure 3.5 (11). Port 5 Port 5 Register bit Symbol (000DH) Read/Write After reset Input mode Note: The input channel selection of A/D Converter is set by A/D Converter mode register ADMOD2.
  • Page 37 TMP96C141AF 3.5.7 Port 6 (P60 - P67) assigned to P60 to P63; PG1, to P64 to P67. Writing 1 in the corresponding bit of the port 6 function register (P6FC) Port 6 is an 8-bit general-purpose I/O port. I/O can be set on enables PG output.
  • Page 38 TMP96C141AF Port 6 Register Figure 3.5 (14). Registers for Port 6 TOSHIBA CORPORATION...
  • Page 39 TMP96C141AF 3.5.8 Port 7 (P70 - P73) 71 as an 8-bit timer output (TO1), Port 72 as a PWM0 output (TO2), and Port 73 as a PWM1 output (TO3) pin. Writing 1 in Port 7 is a 4-bit general-purpose I/O port. I/O can be set on bit the corresponding bit of the Port 7 function register (P7FC) basis.
  • Page 40 TMP96C141AF Figure 3.5 (16). Registers for Port 7 TOSHIBA CORPORATION...
  • Page 41 TMP96C141AF 3.5.9 Port 8 (P80 - P83) clocks, an output for 16-bit timer F/F 4, 5 and 6 output, and an input for INT0. Writing 1 in the corresponding bit of the Port 8 Port 8 is an 8-bit general-purpose I/O port. I/O can be set on a function register (P8FC) enables those functions.
  • Page 42 TMP96C141AF an INT0 pin for external interrupt request input. P87 (INT0) Port 87 is a general-purpose I/O port, and also used as Figure 3.5 (18). Port 87 TOSHIBA CORPORATION...
  • Page 43 TMP96C141AF Figure 3.5 (19). Registers for Port 8 TOSHIBA CORPORATION...
  • Page 44 TMP96C141AF 3.5.10 Port 9 (P90 - P95) Resetting resets the function register value to 0 and sets all bits to ports. Port 9 is a 6-bit general-purpose I/O port. I/Os can be set on a bit basis. Resetting sets Port 9 to an input port and connects a Port 90 and 93 (TXD0/TXD1) pull-up resistor.
  • Page 45 TMP96C141AF Ports 91 and 94 (RXD0, 1) input pins for serial channels. Ports 91 and 94 are I/O ports, and also used as RXD Figure 3.5 (21). Ports 91 and 94 Port 92 (CTS/SCKL0) for serial channel0; additionally, the CTS0 pin, and also as a SCKL0 I/O pin.
  • Page 46 TMP96C141AF Port 95 (SCLK) an SCLK I/O pin for serial channel 1. Port 95 is a general-purpose I/O port. It is also used as Figure 3.5 (23). Port 95 TOSHIBA CORPORATION...
  • Page 47 TMP96C141AF Figure 3.5 (24). Registers for Port 9 TOSHIBA CORPORATION...
  • Page 48 Setting this bit to 0 accesses the memory in 16-bit data bus mode; set- TMP96C141AF has a built-in chip select/wait controller used ting it to 1 accesses the memory in 8-bit data bus to control chip select (CS0 - CS2 pins), wait (WAIT pin), and mode.
  • Page 49 TMP96C141AF Table 3.6 (1) Chip Select/Wait Control Register Code Name Address B0SYS B0CAS B0BUS B0W1 B0W0 B0C1 B0C0 Block0 CS/WAIT B0CS 0068H control 1 : CS/CAS 1 : SYSTEM 0 : CSO 0 : 16-bit 00 : 2WAIT 00 : 7F00H ~ 7FFFH...
  • Page 50 TMP96C141AF Table 3.6 (2) Dynamic Bus Sizing CPU Data Operand Operand Memory CPU Address Data Size Start Address Data Size D15 - D8 D7 - D0 2n + 0 8 bits 2n + 0 xxxxx b7 - b0 8 bits...
  • Page 51 ROM. After reset, CS2 is enabled in 16-bit bus and are divided differently: 7F00H to 7FFFH is specified for CS0; 2-wait. With the TMP96C141AF, which does not have a built- 480H to 7FFFH, for CS1; and 8000H to 3FFFFFH, for CS2.
  • Page 52 TMP96C141AF 3.6.3 Example of Usage nected to the TMP96C141AF. In this example, a ROM is con- nected using 16-bit Bus; a RAM is connected using 8-bit Bus. Figure 3.6 (1) is an example in which an external memory is con- Figure 3.6 (1).
  • Page 53 TMP96C141AF 3.6.4 How to Start with an 8-Bit Data Bus mode. To start in 8-bit data bus mode, a special operation is required. Operation is as described in the example below: Resetting sets the CS2 pin low due to an internal pull-down resistor;...
  • Page 54 TMP96C141AF 3.7 8-bit Timers stant cycle) output mode (1 timer) The TMP96C141AF contains two 8-bit timers (timers 0 and 1), Figure 3.7 (1) shows the block diagram of 8-bit timer (timer 0 and timer 1). each of which can be operated independently. The cascade Each interval timer consists of an 8-bit up-counter, 8-bit connection allows these timers to be used as 16-bit timer.
  • Page 55 TMP96C141AF Figure 3.7 (1). Block Diagram of 8-Bit Timers (Timers 0 and 1) TOSHIBA CORPORATION...
  • Page 56 TMP96C141AF φ T1, φ T4, φ T16, and φ T256. Prescaler This prescaler can be run or stopped by the timer operation control register TRUN <PRRUN>. Counting This 9-bit prescaler generates the clock input to the 8- starts when <PRRUN> is set to “1”, while the prescaler...
  • Page 57 TMP96C141AF Timer register TREG0 should be enabled or disabled. It is disabled when <DBEN> = 0 and enabled when they are set to This is an 8-bit register for setting an interval time. In the condition of double buffer enable state, the data...
  • Page 58 TMP96C141AF Figure 3.7 (4). Timer Operation Control Register (TRUN) TOSHIBA CORPORATION...
  • Page 59 TMP96C141AF Figure 3.7 (5). Timer Mode Control Register (TMOD) TOSHIBA CORPORATION...
  • Page 60 TMP96C141AF Figure 3.7 (6). Timer Flip-Flop Control Register (TFFCR) TOSHIBA CORPORATION...
  • Page 61 TMP96C141AF The operation of 8-bit timers will be described below: Generating interrupts in a fixed cycle (1) 8-bit timer mode To generate timer 1 interrupt at constant intervals using timer 1 (INTT1), first stop timer 1 then set the operation...
  • Page 62 TMP96C141AF Generating a 50% duty square wave pulse TO1 pin at fc = 16MHz, set each register in the following procedures. Either timer 0 or timer 1 may be used, but this example uses The timer flip-flop (TFF1) is inverted at constant inter- timer 1.
  • Page 63 TMP96C141AF Making timer 1 count up by match signal from timer Set the 8-bit timer mode, and set the comparator out- 0 comparator put of timer 0 as the input clock to timer 1. Figure 3.7 (8). Timer 1 Count Up by Timer 0 Output inversion with software Note: The value of timer register cannot be read.
  • Page 64 TMP96C141AF The lower 8 bits of the timer (interrupt) cycle are set by The comparator match signal is output from timer 0 the timer register TREG0, and the upper 8 bits are set each time the up-counter UC0 matches TREG0, where by TREG1.
  • Page 65 TMP96C141AF Figure 3.7 (10). 8-Bit PPG Output Waveforms Figure 3.7 (11). Block Diagram of 8-Bit PPG Output Mode TOSHIBA CORPORATION...
  • Page 66 TMP96C141AF When the double buffer of TREG0 is enabled in this Use of the double buffer makes easy handling of low duty mode, the value of register buffer will be shifted in TREG0 each waves (when duty is varied). time TREG1 matches UC0.
  • Page 67 TMP96C141AF 8-bit PWM Output mode 0>) counter overflow occurs. Up-counter UC0 is cleared when 2n - 1 counter overflow occurs. For example, when n = 6, 6-bit PWM will be output, while This mode is valid only for timer 0. In this mode, maxi- when n = 7, 7-bit PWM will be output.
  • Page 68 TMP96C141AF Figure 3.7 (14) shows the block diagram of this mode. Figure 3.7 (14). Block Diagram of 8-Bit PWM Mode In this mode, the value of register buffer will be shifted in Use of the double buffer makes the handling of small duty TREG0 if 2 - 1 overflow is detected when the double buffer of...
  • Page 69 TMP96C141AF ← TRUN – – – – – Stop timer 0, and clear it to “0”. ← - 1) and select φ T1 as the input clock. TMOD – – Set 8-bit PWM mode (cycle: 2 ← TREG0 Write “48H”.
  • Page 70 3.8 8-Bit PWM Timer Figure 3.8 (1) is a block diagram of 8-bit PWM timer (tim- ers 2 and 3). The TMP96C141AF/TMP96CM40F/TMP96PM40F has two PWM timers consist of an 8-bit up-counter, 8-bit com- built-in 8-bit PWM timers (timers 2 and 3).
  • Page 71 TMP96C141AF Figure 3.8 (1). Block Diagram of 8-Bit PWM Timer 0 (Timer 2) Note: Block diagram for 8-bit PWM timer 1 (timer 3) is the same as the above diagram. TOSHIBA CORPORATION...
  • Page 72 TMP96C141AF The PWM timer uses three input clocks: φ /P1, φ /P4, Prescaler and φ /P16. Like the 9-bit prescaler described in the 8-bit timer Generates input clocks dedicated to PWM timers by section, this prescaler can be counted/stopped using further dividing the fundamental clock (fc) after it has bit 7 <PRRUN>...
  • Page 73 TMP96C141AF TREG2 and TREG3 are controlled double buffer in double buffer enable state, unlike timer mode for enable/disable by P0MOD <DB2EN> and P1MOD timers 0 and 1. <DB3EN> : disabled when <DB2EN>/<DB3EN> = 0, At reset, <DB2EN>/<DB3EN> is initialized to 0 to dis- enabled when <DB2EN>/<DB3EN>...
  • Page 74 TMP96C141AF Figure 3.8 (4). 8-Bit PWM0 Mode Control Register TOSHIBA CORPORATION...
  • Page 75 TMP96C141AF Figure 3.8 (5). 8-Bit PWM1 Mode Control Register TOSHIBA CORPORATION...
  • Page 76 TMP96C141AF Figure 3.8 (6). 8-Bit PWM F/F Control Register TOSHIBA CORPORATION...
  • Page 77 TMP96C141AF Figure 3.8 (7). Timer Operation Control Register (TRUN) TOSHIBA CORPORATION...
  • Page 78 TMP96C141AF The following explains PWM timer operations. Condition 2: • TFF2 is set to 1 when the value in the up-counter (UC2) and the value set in TREG2 match. PWM timer mode • TFF2 is cleared to 0 when a 2 - 1 counter over flow (n = 6, 7, or 8) occurs.
  • Page 79 TMP96C141AF Figure 3.8 (9) is a block diagram of this mode. Figure 3.8 (9). Block Diagram of PWM Timer Mode (PWM0) In this mode, enabling double buffer is very useful. The Using double buffer makes handling small duty waves register buffer value shifts into TREG2 when a 2 -1 overflow...
  • Page 80 TMP96C141AF Example: To output the following PWM waves to TO2 pin using PWM0 at fc = 16MHz. To implement 31.75µs PWM cycle by φ P1 = 0.25µs (@ fc = 16MHz) 31.75µs ÷ 0.25µs = 127 = 2 Consequently, set n to 7.
  • Page 81 TMP96C141AF 8-bit timer mode Generating interrupts at a fixed interval Both PWM timers can be used independently as 8-bit To generate timer 2 interrupt (INTT2) at a fixed interval interval timers. Since both timers operate in exactly the using PWM0 timer, first stop PWM0, then set the oper-...
  • Page 82 TMP96C141AF Generating a 50% square wave value to the timer output pin (TO2). To generate a 50% square wave, invert the timer flip- Example: To output a 3.0µs square wave at fc = flop at a fixed interval and output the timer flip-flop...
  • Page 83 TMP96C141AF This mode is as shown in Figure 3.8 (12) below. Figure 3.8 (12). Block Diagram of 8-Bit Timer Mode TOSHIBA CORPORATION...
  • Page 84 Timer/event counter consists of 16-bit up-counter, two 16-bit timer registers, two 16-bit capture registers (one of them The TMP96C141AF has two (timer 4 and timer 5) multifunc- applies double-buffer), two comparators, capture input con- tional 16-bit timer/event counter with the following operation troller, and timer flip-flop and the control circuit.
  • Page 85 TMP96C141AF Figure 3.9 (1). Block Diagram of 16-Bit Timer (Timer 4) TOSHIBA CORPORATION...
  • Page 86 TMP96C141AF Figure 3.9 (2). Block Diagram of 16-Bit Timer (Timer 5) TOSHIBA CORPORATION...
  • Page 87 TMP96C141AF Figure 3.9 (3). 16-Bit Timer Mode Controller Register (T4MOD) (1/2) TOSHIBA CORPORATION...
  • Page 88 TMP96C141AF Figure 3.9 (4). 16-Bit Controller Register (T4MOD) (2/2) TOSHIBA CORPORATION...
  • Page 89 TMP96C141AF Figure 3.9 (5). 16-Bit Timer 4 F/F Control (T4FFCR) TOSHIBA CORPORATION...
  • Page 90 TMP96C141AF Figure 3.9 (6). 16-Bit Timer Mode Control Register (T5MOD) (1/2) TOSHIBA CORPORATION...
  • Page 91 TMP96C141AF Figure 3.9 (7). 16-Bit Timer Control Register (T5MOD) (2/2) TOSHIBA CORPORATION...
  • Page 92 TMP96C141AF CAP4T6 : Invert when the up-counter value is loaded to CAP4 CAP3T6 : Invert when the up-counter value is loaded to CAP3 EQ7T6 : Invert when up-counter matches TREG7 EQ6T6 : Invert when up-counter matches TREG6 Figure 3.9 (8). 16-Bit Timer 5 F/F Control (T5FFCR)
  • Page 93 TMP96C141AF DB6EN : Double buffer of TREG6 DB4EN : Double buffer of TREG4 Figure 3.9 (9). 16-Bit Timer (Timer 4, 5) Control Register (T45CR) Figure 3.9 (10). Timer Operation Control Register (TRUN) TOSHIBA CORPORATION...
  • Page 94 TMP96C141AF Up-counter (UC4/UC5) timer register TREG5, TREG7. The “clear enable/disable” is set by T4MOD <CLE> and T5MOD <CLE>. UC4/UC5 is a 16-bit binary counter which counts up If clearing is disabled, the counter operates as a free- according to the input clock specified by T4MOD running counter.
  • Page 95 TMP96C141AF • When T4MOD <CAP12M1, 0>/T5MOD matches TREG5/TREG7. (The clearing of up-counter <CAP34M1, 0> = 01 UC4/UC5 can be disabled by setting T4MOD <CLE>/ Data is loaded to CAP1, CAP3 at the rise edge T5MOD <CLE> = 0.) of TI4 pin (also used as P80/INT4) and TI6 pin (also...
  • Page 96 TMP96C141AF ← TRUN – – – – – – Stop timer 4. ← P8CR – – – – – – – Set P80 to input mode. INTET54 ← Enable INTTR5 and sets interrupt level 4, while disables INTTR4. ← T4FFCR Disable trigger.
  • Page 97 TMP96C141AF When the double buffer of TREG4 is enabled in this at match with TREG5. This feature makes easy the handling of mode, the value of register buffer 4 will be shifted in TREG4 low duty waves. Figure 3.9 (12). Operation of Register Buffer Shows the block diagram of this mode.
  • Page 98 TMP96C141AF Application Examples of Capture Function One-Shot Pulse Output from External Trigger Pulse The loading of up-counter (UC4) values into the cap- Set the up-counter UC4 in free-running mode with the ture registers CAP1 and CAP2, the timer flip-flop TFF4...
  • Page 99 TMP96C141AF Setting Example: To output 2ms one-shot pulse with 3ms delay to the external trigger pulse to TI4 pin. Keep counting (Free-running). Count with φ T1. Main setting ← T4MOD – – Load the up-counter value into CAP1 at the rise edge of TI4 pin input.
  • Page 100 TMP96C141AF Figure 3.9 (15). One-Shot Pulse Output (without Delay) Frequency Measurement into the capture register CAP1 at the rise edge of the timer flip-flop TFF1 of 8-bit timers (Timer 0 and Timer 1), and into CAP2 at its fall edge.
  • Page 101 TMP96C141AF Pulse Width Measurement external trigger pulse respectively. The interrupt INT4 occurs at the falling edge of TI4. The pulse width is obtained from the difference This mode allows measuring the “H” level width of an between the values of CAP1 and CAP2 and the internal external pulse.
  • Page 102 TMP96C141AF Figure 3.9 (18). Time Difference Measurement (5) Different Phased Pulses Output Mode When the value in up-counter UC4 and the value in TREG4 (TREG5) match, the value in TFF4 (TFF5) is inverted and output to TO4 (TO5). In this output mode, signals with any different phase can be This mode can only be used by 16-bit timer 4.
  • Page 103 3.10 Stepping Motor Control/Pattern Generation Port the PG port. PG0 and PG1 can be used independently. The TMP96C141AF has two channels (PG0 and PG1) of 4-bit All PG operate in the same manner except the following hardware stepping motor control/pattern generation (herein...
  • Page 104 TMP96C141AF Figure 3.10 (2a). Pattern Generation Control Register (PG01CR) TOSHIBA CORPORATION...
  • Page 105 TMP96C141AF Figure 3.10 (2b). Pattern Generation Control Register (PG01CR) TOSHIBA CORPORATION...
  • Page 106 TMP96C141AF PG0REG bit Symbol PG03 PG02 PG01 PG00 SA03 SA02 SA01 SA00 (004CH) Read/Write After reset Undefined Function Pattern Generation 0 (PG0) output latch register Shift alternate register 0 (Reading the P6 that is set to the PG port allows to read-out.)
  • Page 107 TMP96C141AF Figure 3.10 (5). 16-bit Timer Trigger Control Register (T45CR) TOSHIBA CORPORATION...
  • Page 108 TMP96C141AF Figure 3.10 (6). Connection of Timer and Pattern Generator (1) Pattern Generation Mode In this mode, set PG01CR <PG0M> and <PG1M> to 1, and PG01CR <CCW0> and <CCW1> to 0. The output of this pattern generator is output to port 6;...
  • Page 109 TMP96C141AF ↑ Shift due to the shift trigger from timer Figure 3.10 (7). Pattern Generation Mode Block Diagram (PG0) In this pattern generation mode, only writing the output mode. Accordingly, the data shifted by trigger signal from a latch is disabled by hardware, but other functions do the same timer must be written before the next trigger signal is output.
  • Page 110 TMP96C141AF (2) Stepping Motor Control Mode Figure 3.10 (8) and Figure 3.10 (9) show the output waveforms of 4-phase 1 excitation and 4-phase 2 excita- 4-phase 1-Step/2-Step Excitation tion, respectively when channel 0 (PG0) is selected. ↑ Initial value of PG0REG ← 0100 x x x x bn indicates the initial value of PG0REG ←...
  • Page 111 TMP96C141AF ↑ Initial value of PG0REG ← 0100 x x x x Figure 3.10 (9). Output Waveforms of 4-Phase 2-Step Excitation (Normal Rotation) The operation when channel 0 is selected is 1-step excitation will be selected when only one bit is set explained below.
  • Page 112 TMP96C141AF 4-Phase 1-2 Step Excitation phase 1 -2 step excitation when channel 0 is selected. Figure 3.10 (11) shows the output waveforms of 4- ↑ Initial value of PG0REG ← 11001000 Note: bn denotes the initial value of PG0REG ← b7 b6 b5 b4 b3 b2 b1 b0 Normal Rotation ↑...
  • Page 113 TMP96C141AF The initialization for 4-phase 1-2 step excitation is as example, to change the output waveform shown in Fig- follows: ure 3.10 (11) into negative logic, change the initial value By rearranging the initial value “b7 b6 b5 b4 b3 b2 to “00110111”.
  • Page 114 TMP96C141AF Setting example: To drive channel 0 (PG0) by 4-phase 1-2 timer 0 is selected, set each register as follows: step excitation (normal rotation) when ← TRUN – – – – – – Stop timer 0, and clears it to zero.
  • Page 115 TMP96C141AF (4) Application of PG and Timer Output PPG mode will be explained below. To drive a stepping motor, in addition to the value of each phase (PG output), synchronizing signal is often required at the As explained in “Trigger signal from timer”, the timing to shift timing when excitation is changed over.
  • Page 116 3.11 Serial Channel as well as for I/O extension. The serial channel has the following operation modes: The TMP96C141AF contains two serial I/O channels for full duplex asynchronous transmission (UART) I/O interface mode Mode 0: To transmit and receive I/O data as well as (channel 1 only) the synchronizing signal SCLK for extending I/O.
  • Page 117 TMP96C141AF The serial channel has a buffer register for transmitting detected to be normal at least twice in three samplings. and receiving operations, in order to temporarily store trans- When the transmission buffer becomes empty and mitted or received data, so that transmitting and receiving requests the CPU to send the next transmission data, or when operations can be done independently (full duplex).
  • Page 118 TMP96C141AF Note: There is SC1MOD (56H) in Channel 1 Figure 3.11 (2). Serial Mode Control Register (Channel 0, SC0MOD) TOSHIBA CORPORATION...
  • Page 119 TMP96C141AF Note: Serial control register for channel 1 is SC1CR (55H). As all error flags are cleared after reading, do not test only a single bit with a bit-testing instruction. Figure 3.11 (3). Serial Control Register (Channel, SC0CR) TOSHIBA CORPORATION...
  • Page 120 TMP96C141AF Note: As all error flags are cleared after reading, do not test only a single bit with a bit-testing instruction. Figure 3.11 (4). Serial Channel Control (Channel 0, BR0CR) (Transmission) SC0BUF (50H) (Receiving) Figure 3.11 (5). Serial Transmission/Receiving Buffer Registers (Channel 0, SC0BUF)
  • Page 121 TMP96C141AF Figure 3.11 (6). Serial Mode Control Register (Channel 1, SC1MOD) TOSHIBA CORPORATION...
  • Page 122 TMP96C141AF Note: As all error flags are cleared after reading, do not test only a single bit with a bit-testing instruction. Figure 3.11 (7). Serial Control Register (Channel 1, SC1CR) TOSHIBA CORPORATION...
  • Page 123 TMP96C141AF Note: To use baud rate generator, set TRUN <PRRUN> to “1", putting the prescaler in RUN mode. Figure 3.11 (8). Baud Rate Generator Control Register (Channel 0, BR0CR) (Transmission) SC1BUF (0054H) (Receiving) Figure 3.11 (9). Serial Transmission/Receiving Buffer Registers (Channel 1, SC1BUF)
  • Page 124 TMP96C141AF Figure 3.11 (10). Port 9 Function Register (P9FC) Port 3.11 (11). Port 9 Open Drain Enable Register (ODE) TOSHIBA CORPORATION...
  • Page 125 TMP96C141AF 3.11.2 Configuration Figure 3.11 (12) shows the block diagram of the serial channel 0. Figure 3.11 (12). Block Diagram of the Serial Channel 0 TOSHIBA CORPORATION...
  • Page 126 TMP96C141AF Figure 3.11 (13) shows the block diagram of the serial channel 1. Figure 3.11 (13). Block Diagram of the Serial Channel 1 TOSHIBA CORPORATION...
  • Page 127 TMP96C141AF Baud Rate Generator of these input clocks is selected by the baud rate genera- tor control register BR0CR/BR1CR <BR0CK1, 0/ Baud rate generator comprises a circuit that gener- BR1CK1, 0>. ates transmission and receiving clocks to determine the The baud rate generator includes a 4-bit frequency transfer rate of the serial channel.
  • Page 128 TMP96C141AF Table 3.11 (2) Selection of Transfer Rate (1) (When Timer 0 (Input Clock φ T1) is Used) Unit (Kbps) 12.288MHz 12MHz 9.8304MHz 8MHz 6.144MHz TREG0 76.8 62.5 38.4 31.25 31.25 19.2 19.2 How to calculate the transfer rate (when timer 0 is used):...
  • Page 129 TMP96C141AF 2) Asynchronous Communication (UART) mode the receiving buffer 1. However, unless the receiving buffer 2 (SC0BUF/SC1BUF) is read before all bits of the next data are received by the receiving buffer 1, an over- The receiving control has a circuit for run error occurs.
  • Page 130 TMP96C141AF Handshake function again. The INTTX0 Interrupts are generated, requests the next send data to the CPU. Serial channel 0 has a CTS0 pin. Using Though there is no RTS pin, a hand- this pin, data can be sent in units of one shake function can be easily configured by...
  • Page 131 TMP96C141AF Transmission Buffer bit UART mode and with SC0MOD <RB8>/SC1MOD <RB8> when in 8-bit UART mode. If they are not equal, a Transmission buffer (SC0BUF/SC1BUF) shifts to and parity error occurs, and SC0CR <PERR>/SC1CR sends the transmission data written from the CPU from <PERR>...
  • Page 132 TMP96C141AF 2) I/O Interface mode SCLK output mode Immediately after rise of last SCLK signal (See Figure 3.11 (19) ). Transmission interrupt timing Immediately after rise of last SCLK signal (rising mode), or immediately after fall in falling mode SCLK input mode (See Figure 3.11 (20)).
  • Page 133 TMP96C141AF Transmission time the CPU writes data in the transmission buffer. When all data is output, INTES1 <ITX1C> will be set to generate INTTX1 interrupt. In SCLK output mode, 8-bit data and synchronous clock are output from TxD pin and SCLK pin, respectively, each Figure 3.11 (19) Transmitting Operation in I/O Interface Mode (SCLK Output Mode)
  • Page 134 TMP96C141AF Receiving <IRX1C> is cleared by reading the received data. When 8-bit data are received, the data will be trans- ferred in the receiving buffer 2 (SC1BUF) at the timing In SCLK output mode, synchronous clock is output shown below, and INTES1 <IRX1C> will be set again from SCLK pin and the data is shifted in the receiving to generate INTRX1 interrupt.
  • Page 135 TMP96C141AF Mode 1 (7-bit UART Mode) and even parity or odd parity is selected by SC0CR <EVEN> /SC1CR <EVEN> when <PE> is set to “1” (enable). The 7-bit mode can be set by setting serial channel mode register SC0MOD <SM1, 0> /SC1MOD <SM1, 0>...
  • Page 136 TMP96C141AF Main setting ← P9CR – – – – – Select P91 (RxD) as the input pin. ← SC0MOD – Enable receiving in 8-bit UART mode. ← SC0CR Add an odd parity. ← BR0CR Set transfer rate at 9600 bps.
  • Page 137 TMP96C141AF Protocol The master controller transmits one-frame data including the 8-bit select code for the slave control- Select the 9-bit UART mode for master and slave lers. The MSB (bit 8) <TB8> is set to “1”. controllers. Set SC0MOD <WU>/SC1MOD <WU> bit of each slave controller to “1”...
  • Page 138 TMP96C141AF the internal clock φ 1 (fc/2) as the Setting Example: To link two slave controllers serially transfer clock. with the master controller, and use Since serial channels 0 and 1 operate in exactly the way, channel 0 is used for the purposes of explanation.
  • Page 139 3.12 Analog/Digital Converter verter. The 4-channel analog input pins (AN3 to AN0) are The TMP96C141AF contains a high-speed analog/digital con- shared by input-only P5 and so can be used as input port. verter (A/D converter) with 4-channel analog input that features 10-bit successive approximation.
  • Page 140 TMP96C141AF Figure 3.12 (2). A/D Control Register TOSHIBA CORPORATION...
  • Page 141 TMP96C141AF ADREG0L bit Symbol ADR01 ADR00 (0060H) Read/Write After reset Undefined Function Lower 2 bits of A/D result for AN0 are stored. ADREG0H bit Symbol ADR09 ADR08 ADR07 ADR06 ADR05 ADR04 ADR03 ADR02 (0061H) Read/Write After reset Undefined Function Upper 8 bits of A/D result for AN0 are stored.
  • Page 142 TMP96C141AF ADREG2L bit Symbol ADR21 ADR20 (0064H) Read/Write After reset Undefined Function Lower 2 bits of A/D result for AN2 are stored. ADREG2H bit Symbol ADR29 ADR28 ADR27 ADR26 ADR25 ADR24 ADR23 ADR22 (0065H) Read/Write After reset Undefined Function Upper 8 bits of A/D result for AN2 are stored.
  • Page 143 TMP96C141AF 3.12.1 Operation A/D Conversion Speed Selection Analog Reference Voltage There are two A/D conversion speed modes: high speed mode and low speed mode. The selection is executed by ADMOD <ADCS> register. High analog reference voltage is applied to the VREF pin, and low analog reference voltage is applied to When reset, ADMOD <ADCS>...
  • Page 144 3.13 Watchdog Timer (Runaway Detecting Timer) watchdog timer detects a malfunction, it generates a non- maskable interrupt to notify the CPU of the malfunction, and The TMP96C141AF is containing watchdog timer of Runaway outputs 0 externally from watchdog timer out pin WDTOUT to detecting.
  • Page 145 TMP96C141AF 3.13.1 Configuration Figure 3.13 (1) shows the block diagram of the watchdog timer (WDT). Figure 3.13 (1). Block Diagram of Watchdog Timer TOSHIBA CORPORATION...
  • Page 146 TMP96C141AF The watchdog timer is a 22-stage binary counter which be reset. The watchdog timer out pin is set to 1 by clearing the uses φ (fc/2) as the input clock. There are four outputs from the watchdog timer (by writing a clear code 4EH in the WDCR reg-...
  • Page 147 TMP96C141AF 3.13.2 Control Registers To disable, it is necessary to clear this bit to “0” and write the disable code (B1H) in the watchdog timer Watchdog timer WDT is controlled by two control registers control register WDCR. This makes it difficult for the WDMOD and WDCR.
  • Page 148 TMP96C141AF Figure 3.13 (4). Watchdog Timer Mode Register TOSHIBA CORPORATION...
  • Page 149 TMP96C141AF Figure 3.13 (5). Watchdog Timer Control Register TOSHIBA CORPORATION...
  • Page 150 TMP96C141AF 3.13.3 Operation ation by an anti-malfunction program. By connecting the watchdog timer out pin to peripheral devices’ resets, a CPU The watchdog timer generates interrupt INTWD after the malfunction can also be acknowledged to other devices. detecting time set in the WDMOD <WDTP1, 0> register and The watchdog timer restarts operation immediately after outputs a low level signal.
  • Page 151 TMP96C141AF 4. Electrical Characteristics 4.1 Absolute Maximum (TMP96C141AF) Symbol Parameter Rating Unit Power Supply Voltage -0.5 ~ 6.5 V IN Input Voltage -0.5 ~ V + 0.5 Σ IOL Output Current (total) Σ IOH Output Current (total) -100 ° Power Dissipation (Ta = 70 °...
  • Page 152 TMP96C141AF ° 4.3 AC Electrical Characteristics (TMP96C141AF) V = 5V±10%, Ta = -20 ~ 70 C (4MHz ~ 20MHz) Variable 16MHz 20MHz Symbol Parameter Unit Osc. Period (= x) 62.5 CLK width 2x - 40 60.0 A0 - 23 Valid→CLK Hold 0.5x - 20...
  • Page 153 TMP96C141AF (1) Read Cycle TOSHIBA CORPORATION...
  • Page 154 TMP96C141AF (2) Write Cycle TOSHIBA CORPORATION...
  • Page 155 TMP96C141AF 4.4 A/D Conversion Characteristics (TMP96C141AF) = 5V±10% TA = -20 ~ 70°C Symbol Parameter Unit Analog reference voltage - 1.5 Analog reference voltage Analog input voltage range Analog current for analog reference voltage ±1.5 (TBD) ±4.0 Low speed conversion mode 4 ≤...
  • Page 156 TMP96C141AF 4.7 Interrupt Operation = 5V±10% Ta = -20 ~ 70°C Variable 16MHz 20MHz Symbol Parameter Unit NMI, INT0 Low level pulse width INTAL NMI, INT0 High level pulse width INTAH INT4 ~ INT7 Low level pulse width 8x + 100...
  • Page 157 TMP96C141AF 4.8 Timing Chart for I/O Interface Mode TOSHIBA CORPORATION...
  • Page 158 TMP96C141AF 4.9 Timing Chart for Bus Request (BUSRQ)/BUS Acknowledge (BUSAK) Variable 16MHz 20MHz Symbol Parameter Unit BUSRQ setup time for CLK CLK→BUSAK falling edge 1.5x + 120 CBAL CLK→BUSAK rising edge 0.5x + 40 CBAH Output buffer is off to BUSAK BUSAK output buffer is on.
  • Page 159 TMP96C141AF 4.10 Interrupt Operation = 5V, Ta = -25°C, unless otherwise noted TOSHIBA CORPORATION...
  • Page 160 TMP96C141AF 5. Table of Special Function Registers (1) I/O port (2) I/O port control (SFRs) (3) Timer control (SFR; Special Function Register) (4) Pattern Generator control The special function registers (SFRs) include the I/O ports and peripheral control registers allocated to the 128-byte (5) Watch Dog Timer control addresses from 000000H to 00007FH.
  • Page 161 TMP96C141AF Table 5 I/O Register Address Map Address Name Address Name Address Name Address Name 000000H P0 20H TRUN 40H TREG6L 60H ADREG0L 1H P1 41H TREG6H 61H ADREG0H 2H P0CR 22H TREG0 42H TREG7L 62H ADREG1L 23H TREG1 43H TREG7H...
  • Page 162 TMP96C141AF (1) I/O Port Symbol Name Address PORT0 Input mode Undefined PORT1 Input mode PORT2 Input mode PORT3 Input mode Output mode PORT4 Input mode PORT5 Input mode PORT6 Input mode PORT7 Input mode PORT8 Input mode PORT9 Input mode Note: When P30 pin is defined as RD signal output mode (P30F = 1), clearing the output latch register P30 to “0”...
  • Page 163 TMP96C141AF (2) I/O Port Control (1/2) Symbol Name Address P07C P06C P05C P04C P03C P02C P01C P00C PORT0 (Prohibit P0CR Control RMW) 0 : IN 1 : OUT (When external access, set as AD7 - 0 and cleared to “0".)
  • Page 164 TMP96C141AF I/O Port Control (2/2) Symbol Name Address P67C P66C P65C P64C P63C P62C P61C P60C PORT6 (Prohibit P6CR Control RMW) 0 : IN 1 : OUT P73C P72C P71C P70C PORT7 (Prohibit P7CR Control RMW) 0 : IN 1 : OUT...
  • Page 165 TMP96C141AF (3) Timer Control (1/4) Symbol Name Address PRRUN T5RUN T4RUN P1RUN P0RUN T1RUN T0RUN Timer TRUN Control Prescaler and Timer Run/Stop CONTROL 0 : Stop and Clear 1 : Run (Count up) – 8bit Timer (Prohibit TREG0 Register 0 RMW) Undefined...
  • Page 166 TMP96C141AF Timer Control (2/4) Symbol Name Address FF3C1 FF3C0 FF3TRG1 FF3TRG0 FF2C1 FF2C0 FF2TRG1 FF2TRG0 00 : Don’t care 00 : Prohibit TFF3 00 : Don’t care 00 : Prohibit TFF2 PFFCR Flip-flop 01 : Set TFF3 Inverted 01 : Set TFF2...
  • Page 167 TMP96C141AF Timer Control (3/4) Symbol Name Address TFF5C1 TFF5C0 CAP2T4 CAP1T4 EQ5T4 EQ4T4 TFF4C1 TFF4C0 16bit Timer 4 Flip-flop T4FFCR Control 00 : Invert TFF5 TFF4 Invert Trigger Source Clock 01 : Set TFF5 0 : Trigger Disable 00 : Invert TFF4...
  • Page 168 TMP96C141AF Timer Control (4/4) Symbol Name Address CAP4T6 CAP3T6 EQ7T6 EQ6T6 TFF6C1 TFF6C0 16bit Timer 5 T5FFCR Flip-flop 00 : Invert TFF6 TFF6 Invert Trigger Control 01 : Set TFF6 0 : Trigger Disable 10 : Clear TFF6 1 : Trigger Enable 11 : Don’t care...
  • Page 169 TMP96C141AF (6) Serial Channel (1/2) Symbol Name Address Serial SC0BUF Channel 0 R (Receiving)/W (Transmission) Buffer Undefined EVEN OERR PERR FERR – – R (Cleared to 0 by reading) Serial SC0CR Channel 0 1 : Error Control Parity 1: Input...
  • Page 170 TMP96C141AF Serial Channel (2/2) Symbol Name Address – BR1CK1 BR1CK0 BR153 BR152 BR151 BR150 Baud Rate BR1CR 00 : φ t0 Control (fc/4) Set frequency divisor 01 : φ t2 (fc/16) Fix at “0” 0 ~ F 10 : φ t8 (fc/64) (“1”...
  • Page 171 TMP96C141AF (8) Interrupt Control (1/2) TOSHIBA CORPORATION...
  • Page 172 TMP96C141AF Interrupt Control (2/2) Symbol Name Address µ DMA0 start vector DMA 0 DMA0V8 DMA0V7 DMA0V6 DAM0V5 DMA0V4 DMA0V request (Prohibit Vector RMW) µ DMA1 start vector DMA 1 DMA01V8 DMA1V7 DMA1V6 DAM1V5 DMA1V4 DMA1V request (Prohibit Vector RMW) µ DMA2 start vector...
  • Page 173 TMP96C141AF (9) Chip Select/Wait Controller Symbol Name Address B0SYS B0CAS B0BUS B0W1 B0W0 B0C1 B0C0 Block 0 CS/WAIT B0CS (Prohibit control 00 : 2WAIT 00 : 7F00H ~ 7FFFH RMW) register 1 : CS 1 : SYSTEM 0 : CS0...
  • Page 174 TMP96C141AF 6. Port Section Equivalent Circuit Diagram STOP: This signal becomes active “1” when the hold mode setting register is set to the STOP mode and the CPU • Reading The Circuit Diagram executes the HALT instruction. When the drive enable Basically, the gate singles written are the same as bit [DRIVE] is set to “1”, however, STP remains at “0”.
  • Page 175 TMP96C141AF • P42 (CS2, CAS2) • P5 (AN0 ~ 3) • P87 (INT0) • P90 (TXD0), P93 (TXD1) TOSHIBA CORPORATION...
  • Page 176 TMP96C141AF • NMI • WDTOUT • CLK • EA, AM8/16 • ALE • RESET TOSHIBA CORPORATION...
  • Page 177 TMP96C141AF • X1, X2 • VREF, AGND TOSHIBA CORPORATION...
  • Page 178 TMP96C141AF 7. Guidelines and Restrictions external oscillator. As a result, it takes warming up time from inputting the releasing request to outputting the system clock. Special Expression High Speed µ DMA (DRAM) refresh mode) Explanation of a built-in I/O register: Register When the bus is released (BUSAK = “0”) for waiting to...

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