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TB1MOD
Bit symbol
(1192H)
Read/Write
After Reset
Prohibit
Function
Always write "0".
read-
modify-
write
TMRB1 source clock
Control clearing for up counter (UC12)
Capture/interrupt timing
Software capture
TMRB1 Mode Register
7
6
5
−
−
TB1CP0I
R/W
W*
0
0
1
Software
capture control
0: Execute
1: Undefined
00
01
<TB1CLK1:0>
10
11
0
<TB1CLE>
1
00
01
<TB1CPM1:0>
10
11
0
<TB1CP0I>
1
Figure 3.13.5 Register for TMRB (3)
92CZ26A-304
4
3
TB1CPM1 TB1CPM0
TB1CLE
R/W
0
0
Capture timing
Control
00:Disable
Up counter
INT7 occurs at
0:Disable
rising edge
1: Enable
01:TB1IN0 ↑
INT7 occurs at
rising edge
10: TB1IN0 ↑ TB1IN0 ↓
INT7 occurs at
falling edge
11: TA3OUT ↑
TA3OUT ↓
INT7 occurs at rising
edge
TB1IN0 pin input
φT1
φT4
φT16
Disable
Enable clearing by match with
TB1RG1H/L
Capture control
Disable
Capture to TB1CP0H/L at rising edge of TB1IN0
Capture to TB1CP0H/L at rising edge of TB1IN0
Capture to TB1CP1H/L at falling edge of TB1IN0
Capture to TB1CP0H/L at rising edge of TA3OUT
Capture to TB1CP1H/L at falling edge of TA3OUT
The value of up counter is captured to TB1CP0H/L
Undefined (Note)
TMP92CZ26A
2
1
0
TB1CLK1
TB1CLK0
0
0
0
TMRB1 source clock
00: TB1IN0 input
01: φT1
10: φT4
11: φT16
INT7 control
INT7 occurs at the rising
edge of TB1IN0
INT7 occurs at the rising
edge of TB1IN0
INT7 occurs at the rising
edge of TB1IN0
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