Toshiba H1 Series Data Book page 95

(3) HDMACAn (DMA Transfer Count A Setting Register)
The HDMACAn register is used to set the number of times a DMA transfer is to be
performed by one DMA request. HDMACAn contains 16 bits and can specify up to 65536
transfers (0001H = one transfer, FFFFH = 65535 transfers, 0000H = 65536 transfers). Even
when the transfer count A is updated by DMA execution, HDMACAn is not updated.
HDMACA0 to HDMACA5 have the same configuration.
HDMACAn
bit Symbol DnCA7
Read/Write
After reset
Function
bit Symbol DnCA15
Read/Write
After reset
Function
Channel 0
Channel 1
Channel 2
Channel 3
Channel 4
Channel 5
Note: Read-modify-write instructions can be used on all these registers.
HDMACAn Register
7 6 5
DnCA6 DnCA5
0 0 0
15 14 13
DnCA14 DnCA13
0 0 0
Transfer count A Transfer count A
[15: 8] [7: 0]
HDMACA0
(0909H) (0908H)
HDMACA1
(0919H) (0918H)
HDMACA2
(0929H) (0928H)
HDMACA3
(0939H) (0938H)
HDMACA4
(0949H) (0948H)
HDMACA5
(0959H) (0958H)
Figure 3.6.4 HDMACAn Register
92CZ26A-92
4 3
DnCA4 DnCA3
R/W
0 0
Transfer count A [7:0] for DMAn
12 11
DnCA12 DnCA11
R/W
0 0
Transfer count A [15:8] for DMAn
TMP92CZ26A
2 1 0
DnCA2 DnCA1 DnCA0
0 0 0
10 9 8
DnCA10 DnCA9 DnCA8
0 0 0