Toshiba H1 Series Data Book page 32

The following is a setting example for PLL0-starting and PLL0-stopping.
(Example-1) PLL0-starting
PLLCR0 EQU 10E8H
PLLCR1 EQU 10E9H
LD (PLLCR1),1XXXXXXXXB
LUP: BIT 5,(PLLCR0)
JR Z,LUP
LD (PLLCR0), X1XXXXXXB
X: Don't care
<PLL0>
<FCSEL>
PLL output: f
PLL
Lockup timer
<LUPFG>
System clock f
SYS
(Example-2) PLL0-stopping
PLLCR0 EQU 10E8H
PLLCR1 EQU 10E9H
LD (PLLCR0),X0XXXXXXB
LD (PLLCR1),0XXXXXXXB
X: Don't care
<FCSEL>
<PLL0>
PLL0 output: f
PLL
System clock f
SYS
Note) PLL1 operates as well.
;
Enables PLL0 operation and starts lock-up
;
Detects end of lock-up
;
; Changes fc from 10 MHz to 60 MHz.
Counts up by f
OSCH
During lock-up
Starts PLL0 operation and
Starts lock-up.
; Changes fc from 60 MHz to10 MHz.
; Stop PLL
Changes from 60MHz to 10 MHz.
92CZ26A-29
After lock-up
Changes from 10MHz to 60MHz.
Ends of lock-up
Stops PLL0 operation .
TMP92CZ26A
.