Toshiba H1 Series Data Book page 232

(4) Read data shift function
If the AC specifications of the SDRAM cannot be satisfied when data is read from the
SDRAM, the read data can be latched in a port circuit so that the CPU can read the data in
the next state. When this read data shift function is used, the read cycle requires additional
one state. The write cycle is not affected. The timing waveforms for various cases are shown
below.
(a) 1-word read, the read data shift function disabled (SDACR<SRCS> = "0")
SDCLK
NOP
COMMAND
Row Address
A15-A0
D15-D0
Internal system
clock
Internal dat bus
(b) 1-word read, the read data shift function enabled (SDACR<SRDS> = "1",
<SRDSCK>="0")
SDCLK
NOP
COMMAND
Row Address
A15-A0
D15-D0
Internal system
clock
ク ク
Internal data bus
ACTIVE READ
ColumnAddress
ACTIVE READ
External data latch
92CZ26A-229
NOP NOP
Row Address
DIN1
DIN1
CPU data read
NOP NOP
ColumnAddress
DIN1
DIN1
CPU data read
TMP92CZ26A
ACTIVE READ
Column
Address
NOP ACTIVE
Row Address