Toshiba H1 Series Data Book page 208

32bit micro controller tlcs-900/h1 series
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Address memory map
000000H
Internal I/O, RAM
COMMON-X
(2MB)
200000H
LOCAL-X
(2MB)
400000H
LOCAL-Y
(2MB)
600000H
COMMON-Y
(2MB)
800000H
LOCAL-Z
(4MB)
C00000H
COMMON-Z
(4MB)
FFFF00H
Vector area
FFFFFFH
Note1: CSZA is a chip-select for not only bank0 to 127 of LOCAL-Z but also COMMON-Z.
Note2: In case of connect SDRAM to Y-area, 64MB(2MB×32) is maximum
Figure 3.9.1Recommendation memory map for maximum specification (Logical address)
ND
0
CE
ND
1
CE
CSXA
512MB(2MB× 256)
・ ・・ 15
Bank 0
1
2
3
・ ・・ 15
Bank 0
1
2
3
: 64MB*(SDRAM case 2MB× 32) or
SDCS
・ ・・ 127 128 ・ ・・ 255 ・ ・・ 384 ・ ・・ 511
3
Bank 0
1
2
pin (Note)
CSZA
512MB(4MB× 128)
Internal area
:
Overlapped with CO MMON-Area and disabled setting as LOCAL-area.
:
92CZ26A-205
pin (512MB)
pin (512MB)
512MB(2MB× 256)
・ ・・
255 256 ・ ・
・ ・・
63
pin: 128MB (2MB× 64)
CS
1
・ ・・
pin
CSZB
TMP92CZ26A
Memory controller
setting
CSXB
CS3-area
4MB
511
CS1-area
4MB
CS2-area
8MB
pin
CSZD

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