Toshiba H1 Series Data Book page 550

32bit micro controller tlcs-900/h1 series
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TFT 256-color (1-pixel display data = 8-bit memory data (R: 3 bits, G: 3 bits, B: 2 bits)
Display Memory
Address 0
LSB
D0
0
1
2 3
4 5 6
R0
G0
B0
Address 4
LSB
D0
32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63
R4
G4
B4
12bit (TFT)
0(R0) → 12(R1) ...
LD0
1(R0) → 13(R1) ...
LD1
2(R0) → 14(R1) ...
LD2
3(G0) → 15(G1) ...
LD3
4(G0) → 16(G1) ...
LD4
5(G0) → 17(G1) ...
LD5
6(B0) → 18(B1) ...
LD6
7(B0) → 19(B1) ...
LD7
Figure 3.19.7 Memory Map Image and Data Output in TFT 256-Color Mode
Address 1
7
8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
R1
G1
B1
Address 5
R5
G5
B5
Address 2
R2
G2
B2
Address 6
R6
G6
B6
92CZ26A-547
TMP92CZ26A
Address 3
MSB
D31
R3
G3
B3
Address 7
MSB
D31
R7
G7
B7

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