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Table 3.7.2 I/O Port and Specifications (4/4)
Port
Pin name
Port R
PR0 to PR3
PR0 to PR3
PR0
PR1
PR2
PR3
Port T
PT0 to PT7
PT0 toPT7
PT0 to PT7
Port U
PU0 to PU7
PU0 to PU7
PU0 to PU7
PU7
Port V
PV0 to PV2
PV0 to PV4
PV6 to PV7
PV6 to PV7
PV6 to PV7
PV0
PV6
PV7
Port W
PW0 to PW7
PW0 to PW7
Port X
PX5, PX7
PX4
PX5, PX7
PX4
PX5
Port Z
PZ0 to PZ7
PZ0
PZ1
PZ2
PZ3
PZ4
PZ5
PZ6
PZ7
Note: When Debug mode, it is set to the Debug pin regardless of port setting.
Specification
Input port
Output port
SPDI Input
SPDO Output
SPCS Output
SPCLK Output
Input port
Output port
LD8 to LD15 Output
Input port
Output port
LD16 to LD23 Output
EO_TRGOUT ( DBGE = "0") Note:
Input port
Output port
Input port
Output port
Output port (Open-drain)
SCLK0 Output
SDA I/O
SDA I/O (Open-drain)
SCL I/O
SCL I/O (Open-drain)
Input port
Output port
Input port
Output port
Output port
CLKOUT Output
LDIV Output
X1USB Input
Input port
Output port
EI_PODDATA ( DBGE = "0") Note:
EI_SYNCLK ( DBGE = "0") Note:
EI_PODREQ ( DBGE = "0") Note:
EI_REFCLK ( DBGE = "0") Note:
EI_TRGIN ( DBGE = "0") Note:
EI_COMRESET ( DBGE = "0") Note:
EO_MCUDATA ( DBGE = "0") Note:
EO_MCUREQ ( DBGE = "0") Note:
92CZ26A-116
TMP92CZ26A
X: Don't care
I/O register
Pn
PnCR
PnFC
PnFC2
X
0
0
X
1
0
X
0
1
X
1
1
X
1
1
X
1
1
X
0
0
X
1
0
X
1
1
X
0
0
X
1
0
X
1
1
X
X
X
X
0
0
X
1
0
X
0
0
X
1
0
X
1
0
X
1
1
X
1
1
X
1
1
X
1
1
X
1
1
X
0
0
X
1
0
X
0
0
X
None
0
X
1
0
0
1
None
1
1
X
0
1
X
0
0
X
1
0
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
None
None
None
None
0
1
None
0
1
0
1
None
None
None
None
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