Toshiba H1 Series Data Book page 654

4.3.3 SDRAM controller AC Characteristics
Parameter
Ref/Active to ref/active
1
command period
Active to precharge
2
command period
Active to read/write
3
command delay time
Precharge to active
4
command period
Active to active
5
command period
6 Write recovery time
7 CLK cycle time
8 CLK high level width
9 CLK low level width
Access time from CLK(CL * = 2)
10-1a
<SRDS>=0(Read data shift OFF)
10-1b
Access time from CLK(CL * = 2)
10-2a
<SRDS>=1(Read data shift ON)
10-2b
11 Output data hold time
12 Data-in set-up time
13 Data-in hold time
14 Address set-up time
15 Address hold time
16 CKE set-up time
17 Command set-up time
18 Command hold time
19 Mode register set cycle time
*CL: CAS latency
AC measuring condition
= 30
SDCLK pin C
L
Symbol
<STRC[2:0]>=000
t
RC
<STRC[2:0]>=110
<STRC[2:0]>=000
t
RAS
<STRC[2:0]>=110
<STRCD>=0
t
RCD
<STRCD>=1
<STRP>=0
t
RP
<STRP>=1
<STRC[2:0]>=000
t
RRD
<STRC[2:0]>=110
<STWR>=0
t
WR
<STWR>=1
t
CK
t
CH
t
CL
t
AC
t
AC
t
OH
1Word/Single t
DS
Burst t
DS
T − 10
t
1Word/Single
DH
t
DH
Burst
t
DH
t
AS
t
AH
t
CKS
t
CMS
t
CMH
t
RSC
= 50 pF
pF, Other pins C
L
92CZ26A-651
Variable
80 MHz 60 MHz
Min Max
T 12.5
7T 87.5
2T 12210 25.0
7T 87.5
T 12.5
2T 25.0
T 12.5
2T 25.0
3T 37.5
7T 87.5
T 12.5
2T 25.0
T 12.5
0.5T − 5 −
0.5T − 3
3.25
0.5T − 5 −
0.5T − 3
3.25
T − 16 −
T − 16
- 3.5
T − 6.5 −
T − 6.5
6
0 0
0.5T − 4
2.25
0.5T − 4
2.25
2.5
0.5T − 6 −
0.5T − 4
2.25
0.5T − 4
2.25
0.5T − 6 −
0.5T − 4
2.25
0.5T − 5 −
0.5T − 3
3.25
0.5T − 5 −
0.5T − 3
3.25
0.5T − 6 −
0.5T − 4
2.25
T 12.5
TMP92CZ26A
Unit
16.6
116.2
33.2
116.2
16.6
33.2
16.6
33.2
49.8
116.2
16.6
33.2
16.6
3.3
−
3.3
−
0.6
−
ns
10.1
−
0
3.3
3.3
6.6
2.3
−
4.3
2.3
−
3.3
−
3.3
−
2.3
−
16.6