Toshiba H1 Series Data Book page 112

Sample 5) Calculation example when using CPU + LCDC + SDRAMC + HDMA
Conditions:
CPU operation speed (f
Display RAM
Display size
Display quality
Refresh rate
HDMA
Calculation example:
t
STOP
LHSYNC [period: S]
t
STOP
LCD driver data transfer time [S]
LHSYNC [cycle S] - LCD driver data transfer time [S] − t
To realize proper LCD display, the maximum time HDMA can occupy the bus at a time (maximum HDMA time)
must be set to 19.8875 [ μ S] or less. Although transferring all 225 Kbytes from the internal RAM to SDRAM requires t
(HDMA) = 9180 [ μ s], the maximum HDMA time should be limited by using the HDMATR register.
Bit Symbol
HDMATR
Read/Write
(097FH)
After reset
Function
Note: Read-modify-write instructions can be used on this register.
By writing "86H" to the HDMATR register, the maximum HDMA time is set to 19.2[μs]
(256 × 6 × (1 / f
Note: To be precise, the bus assert time and RAM access time are added each time the HDMA transfer time is
forcefully terminated at 19.2 [ μ s].
at same time (Worst case)
)
SYS
= ((SegNum × K/8) × t
(LCD)
= ((320 × 24/8) × 1/f
= ((960) × 12.5 [nS]/4) + 12.5 [nS]
= 3.0125 [ μ S]
= 1/70 [Hz]/ (COM+20) = 54.9 [ μ S]
= (((2 + 1) × 4) × 57600) + 28800 + 14400)/f
(HDMA)
= SegNum × (1/fsys) × (LD bus transfer speed)
= 320 × (1/80MHz) × 8 = 32 [ μ S]
= 54.9 [ μ S] − 32 [ μ S] − 3.0125 [ μ S] = 19.8875 [ μ S]
7 6
DMATE DMATR6 DMATR5
0 0
Timer
operation
The value to be set in <DMATR6:0> should be obtained by
0: Disable
1:Enable
)).
SYS
: 80MHz
: Internal RAM
: QVGA (320seg × 240com)
: 16777216 color (TFT)
: 70Hz
: Transfers 225 Kbytes from internal RAM to SDRAM
) + (1/f
[Hz])
LRD SYS
[Hz]/4) + (1/f
SYS SYS
(LCD)
STOP
HDMATR register
5 4 3
DMATR4 DMATR3
R/W
0 0 0
Maximum bus occupancy time setting
"Maximum bus occupancy time / (256/f
"00H" cannot be set.
92CZ26A-109
TMP92CZ26A
[Hz])
[S] = 9180 [ μ S]
SYS
2 1
DMATR2 DMATR1
0 0
)".
SYS
STOP
0
DMATR0
0