Toshiba H1 Series Data Book page 17

3. Operation
This section describes the basic components, functions and operation of the TMP92CZ26A.
3.1 CPU
The TMP92CZ26A contains an advanced high-speed 32-bit CPU (900/H1 CPU)
3.1.1 CPU Outline
900/H1 CPU is high-speed and high-performance CPU based on 900/L1 CPU. 900/H1
CPU has expanded 32-bit internal data bus to process Instructions more quickly.
Outline is as follows:
Table 3.1.1Outline of TMP92CZ26A
Parameter
Width of CPU Address Bus
Width of CPU Data Bus
Internal Operating Frequency
Minimum Bus Cycle
Internal RAM
Internal Boot ROM
Internal I/O
External memory
(SRAM, MASKROM etc.)
External memory
(SDRAM)
External memory
(NAND FLASH)
Minimum Instruction
Execution Cycle
Conditional Jump
Instruction Queue Buffer
Instruction Set
CPU mode
Micro DMA
Hardware DMA
92CZ26A-14
TMP92CZ26A
24-bit
32-bit
Max 80MHz
1-clock access
(12.5ns at 80MHz)
32-bit 2-1-1-1 clock access
32 bit 2-clock access
8-bit,
2-clock access
16-bit,
2-clock access
32-bit,
2-clock access
32-bit,
1-clock access
8-bit,
5 to 6-clock access
8/16-bit 2-clock access
(can insert some waits)
16-bit 1-clock access
8/16-bit 2-clock access
(can inset some waits)
1-clock(12.5ns at 80MHz)
2-clock(25.0ns at 80MHz)
12-byte
Compatible with TLCS-900/L1
(LDX instruction is deleted)
Only maximum mode
8-channel
6-channel
TMP92CZ26A
INTC,SDRAMC,
MEMC,LCDC,
TSI,PORT,
PMC
MMU,USB,
NDFC,SPIC,DMAC
I2S
MAC
MAC
TMRA,TMRB,
SIO,RTC,
MLD/ALM, SBI
CGEAR,ADC,WDT