Toshiba H1 Series Data Book page 426

32bit micro controller tlcs-900/h1 series
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IDLE
Receive IN token
ConfirmToken packet
• PID
• Address
• Endpoint
• Transfer mode
• Error
OK
Confirm Handshake answer
• Confirm STATUS register (Status)
• Confirm DATASET register
OK
Generate DATA PID
• Attach DATA0/DATA1
• Confirm Datasize register
OK
Transmit data
OK
Attach CRC
OK
Wait ACK
to host
Receive ACK
Normal finish transaction
• Clear FIFO
• Clear DATASET register
• Renew toggle bit
• Set STATUS to READY
Figure 3.16.7 Control Flow in UDC (Bulk transfer type (transmission)/Interrupt transfer type (transmission))
Error
Invalid
Stall
FIFO empty
More than MAX
payload
Bit stuff error
Set STATUS at STALL
Time out
• Set STATUS to TX_ERR
• Put back addless pointer of FIFO
92CZ26A-423
Transmit NAK
Transmit STALL
TMP92CZ26A

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