Toshiba H1 Series Data Book page 319

3.14.1 Block Diagram
Prescaler
φT0
2 4 8 16 32
φT2 φT8
Serial clock generation circuit
BR0CR<BR0CK1:0>
φT0
φT2
φT8
φT32
Baud rate generator
f
IO
SCLK0
I/O interface mode
SCLK0
Receive counter
(UART only ÷ 16)
RXDCLK
SC0MOD0
Receive
<RXE>
control
RXD0
Receive buffer 1 (Shift register)
RB8 Receive buffer 2 (SC0BUF)
64
φT32
TA0TRG
(from TMRA0)
BR0CR BR0ADD
<BR0S3:0> <BR0K3:0>
BR0CR
<BR0ADDE>
÷2
SC0MOD0 Serial channel
<WU>
interrupt control
<PE>
Parity control
Error flag
SC0CR
<OERR> <PERR> <FERR>
Internal data bus
Figure 3.14.2 Block Diagram
92CZ26A-316
UART
mode
SC0MOD0 SC0MOD0
<SC1:0> <SM1:0>
I/O interface mode
SC0CR
<IOC>
TXDCLK
SC0CR
<EVEN>
TB8
TMP92CZ26A
SIOCLK
INT request
Transmision
counter
(UART only ÷ 16)
Transmission
control
SC0MOD0
<CTSE>
Transmission buffer (SC0BUF)
INTRX0
INTTX0
CTS0
TXD0