Toshiba H1 Series Data Book page 552

32bit micro controller tlcs-900/h1 series
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TFT 65536-color (16 bpp: R: 5 bits, G: 6 bits, B: 5 bits)
Display Memory
Address 0
LSB
D0
0
1
2 3
4 5 6
R0
Address 4
LSB
D0
32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63
R2
16-bit TFT
0(R0) → 16(R1) ...
LD0
1(R0) → 17(R1) ...
LD1
2(R0) → 18(R1) ...
LD2
3(R0) → 19(R1) ...
LD3
4(R0) → 20(R1) ...
LD4
5(G0) → 21(G1) ...
LD5
6(G0) → 22(G1) ...
LD6
7(G0) → 23(G1) ...
LD7
8(G0) → 24(G1) ...
LD8
9(G0) → 25(G1) ...
LD9
LD10 10(G0) → 26(G1) ...
LD11 11(B0) → 27(B1) ...
LD12 12(B0) → 28(B1) ...
LD13 13(B0) → 29(B1) ...
LD14 14(B0) → 31(B1) ...
LD15 15(B0) → 32(B1) ...
Figure 3.19.9 Memory Map Image and Data Output in TFT 65536-Color Mode
Address 1
7
8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
G0
B0
Address 5
G2
B2
92CZ26A-549
Address 2
R1
G1
Address 6
R3
G3
TMP92CZ26A
Address 3
MSB
D31
B1
Address 7
MSB
D31
B3

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