Toshiba H1 Series Data Book page 505

(2) Setting example for the clock generator (8-bit counter/6-bit counter)
The clock generator generates the reference clock for setting the data transfer speed
and sampling frequency.
bit Symbol
I2S0C
Read/Write
(180AH)
After reset
Function
Bit symbol
(180BH)
Read/Write
After reset
Function
• Setting the transfer clock I2SnCKO
Note: It is recommended that the value to be set in I2SnC<CKn7:0> be an even number. Although it is possible to
• Setting the sampling frequency WS
example.
7 6 5
CK07 CK06 CK05
R/W R/W R/W
0 0 0
Divider value for CK signal (8-bit counter)
15 14 13
WS05
R/W
0
The transfer clock is generated by dividing the clock selected by I2SnCTL
<CLKSn>. An 8-bit counter is provided to divide the source clock by 3 to 256. (The
divider value cannot be set to 1 or 2.)
Note: The transfer clock must not exceed 10 MHz. Make sure that the transfer clock is set to within 10
MHz by an appropriate combination of source clock frequency and divider value.
8-bit counter set value
00000000
00000001
11111111
= 60 MHz and I2SnC<CKn7:0> = 150, the data transfer speed is set as follows:
When f
SYS
I2SnCKO = f /150
SYS
= 60 [MHz]/150 = 400 [kbps]
set an odd number, the clock duty of the CK signal does not become 50%. Setting an odd number causes
the High width of the I2SnCK0 signal to become longer by one f
<EDGE> = 0, the Low width becomes longer than the High width.)
The sampling frequency is set by dividing the transfer clock (CK) described above.
A 6-bit counter is provided to divide the transfer clock by 16 to 64. (The divider
value cannot be set to 1 to 15.)
6-bit counter set value
000000
000001
111111
= 60 MHz, I2SnC<CKn7:0> = 150, and I2SnC<WSn5:0> = 50, the sampling frequency is set as
When f
SYS
follows:
I2SnCKO = f
SYS
= 60 [MHz] / 150 / 50 = 8 [kHz]
Based on the above, the transfer clock is set to 400 kbps, and the sampling frequency is set to 8 kHz in this
92CZ26A-502
4 3
CK04 CK03
R/W R/W
0 0
12 11
WS04 WS03
R/W R/W
0 0
Divider value for WS signal (6-bit counter)
Divider value
256
1
255
Divider value
64
1
63
/ 150 / 50
TMP92CZ26A
2 1 0
CK02 CK01 CK00
R/W R/W R/W
0 0 0
10 9 8
WS02 WS01 WS00
R/W R/W R/W
0 0 0
or f pulse than the Low width. (When
sys PLL