Toshiba H1 Series Data Book page 11

2.2 Pin names and Functions
The names of the input/output pins and their functions are described below.
Number of
Pin name
Pins
D0 to D7 8
P10 to P17
8
D8 to D15
P40 to P47
8
A0 to A7
P50 to P57
8
A8 to A15
P60 to P67
8
A16 to A23
P70 1
RD
P71 1
WRLL
NDRE
P72 1
WRLU
NDWE
P73 1
EA24
P74 1
EA25
P75 1
R/
W
NDR/ B
P76
1
WAIT
P80
1
CS 0
P81 1
CS 1
SDCS
P82 1
CS 2
CSZA
SDCS
P83 1
CS 3
CSXA
P84 1
CSZB
P85 1
CSZC
Table 2.2.1 Pin names and functions (1/6)
I/O
I/O Data: Data bus D0 to D7.
I/O Port 1: I/O port. Input or output is specifiable in units of bit.
I/O Data : Data bus D8 to D15.
Output Port 4: Output port.
Output Address : Address bus A0 to A7.
Output Port 5: Output port.
Output Address : Address bus A8 to A15.
I/O Port 6 : I/O port. Input or output is specifiable in units of bit.
Output Address : Address bus A16 to A23.
Output Port 70 : Output port.
Output Read : Outputs strobe signal to read external memory.
I/O Port 71 : Output port.
Output Write : Outputs strobe signal to write data on pins D0 to D7.
Output NAND Flash read : Outputs strobe signal to read external NAND-Flash.
I/O Port 72 : I/O port.
Output Write : Outputs strobe signal to write data on pins D8 to D15.
Output NAND Flash write : Write enable for NAND Flash.
I/O Port 73 : I/O port.
Output Expanded address 24.
I/O Port 74 : I/O port.
Output Expanded address 25.
I/O Port 75 : I/O port.
Output Read/Write : "High" represents read or dummy cycle and "Low" write cycle.
Input NAND Flash Ready(1) / Busy(0) input.
I/O Port 76: I/O port.
Input Wait: Signal used to request CPU bus wait.
Output Port 80: Output port.
Output Chip select 0: Outputs "Low" when address is within specified address area.
Output Port 81 : Output port
Output Chip select 1: Outputs "Low" when address is within specified address area.
Output Chip select for SDRAM : Outputs "Low" when the address is within SDRAM address area.
Output Port 82 : Output port.
Output Chip select 2: Outputs "Low" when address is within specified address area.
Output Expanded address ZA : Outputs "Low" when address is within specified address area.
Output Chip select for SDRAM : Outputs "0" when the address is within SDRAM address area.
Output Port 83 : Output port.
Output Chip select 3: Outputs "Low" when address is within specified address area.
Output Expanded address XA : Outputs "Low" when address is within specified address area.
Output Port 84 : Output port.
Output Expanded address ZB : Outputs "Low" when address is within specified address area.
Output Port 85 : Output port.
Output Expanded address ZC : Outputs "Low" when address is within specified address area.
92CZ26A-8
Functions
TMP92CZ26A