Toshiba H1 Series Data Book page 336

a. Transmission
In SCLK output mode 8-bit data and a synchronous clock are output on the TXD0 and
SCLK0 pins respectively each time the CPU writes the data to the Transmission Buffer.
When all data is output, INTES0 <ITX0C> will be set to generate the INTTX0 interrupt.
Timing to write
transmisison data
SCLK0 output
(<SCLKS> = 0:
rising edge mode)
SCLK0 output
(<SCLKS> = 1:
falling edge mode)
TXD0
ITX0C
(INTTX0 interrupt
request)
Figure 3.14.13 Transmitting Operation in I/O Interface Mode (SCLK0 Output Mode)
In SCLK Input Mode, 8-bit data is output on the TXD0 pin when the SCLK0 input
becomes active after the data has been written to the Transmission Buffer by the
CPU.
When all data is output, INTES0 <ITX0C> will be set to generate INTTX0
interrupt.
SCLK0 input
(<SCLKS> = 0:
rising edge mode)
SCLK0 input
(<SCLKS> = 1:
falling edge mode)
TXD0
ITX0C
(INTTX0 intterrupt
reqest)
Figure 3.14.14 Transmitting Operation in I/O Interface Mode (SCLK0 Input Mode)
Bit0 Bit1
Bit0 Bit1 Bit5
92CZ26A-333
TMP92CZ26A
Bit6 Bit7
Bit6 Bit7
(Internal clock
timing)