Toshiba H1 Series Data Book page 223

3.10 SDRAM Controller (SDRAMC)
The TMP92CZ26A incorporates an SDRAM controller (SDRAMC) for accessing SDRAM that can
be used as data memory, program memory, or display memory.
The SDRAMC has the following features:
(1) Supported SDRAM
Data rate type
Memory capacity
Number of banks
Data bus width
Read burst length
Write mode
(2) Supported initialization sequence commands
Precharge All command
Eight Auto Refresh commands
Mode Register Set command
(3) Access mode
Burst length
Addressing mode
CAS latency (clock)
Write mode
(4) Access cycles
CPU access cycles
Read cycle
Write cycle
Data size
HDMA access cycles
Read cycle
Write cycle
Data size
LCDC access cycles
Read cycle
Data size
(5) Auto generation of refresh cycles
• Auto Refresh is performed while the SDRAM is not being accessed.
• The Auto Refresh interval is programmable.
• The Self Refresh function is also supported.
Note: The SDRAM address area is determined by the CS1 or CS2 setting of the memory controller. However, the number of
bus cycle states is controlled by the SDRAMC.
: SDR (single data rate) type only
: 16 / 64 / 128 / 256 / 512 Mbits
: 2 banks / 4 banks
: 16 bits
: 1 word / full page
: Single mode / Burst mode
CPU Cycle HDMA Cycle
1 word 1 word or full page selectable
Sequential
2
Single Single or burst selectable
: 1 word, 4-3-3-3 states (minimum)
: Single, 3-2-2-2 states (minimum)
: 1 byte / 1 word / 1 long-word
: 1 word, 4-3-3-3 states / full page, 4-1-1-1 states (minimum)
: Single, 3-2-2-2 states (minimum) / burst, 2-1-1-1 states (minimum)
: 1 byte / 1 word / 1 long-word
: Full page, 4-1-1-1 states (minimum)
: 1 word
92CZ26A-220
Sequential
2
TMP92CZ26A
LCDC Cycle
Full page
Sequential
2