Toshiba H1 Series Data Book page 498

• Note of FIFO buffer
There are following notes in this SPIC.
1) Transmit
・ Data is overwritten if write data with condition transmit FIFO buffer is FULL.
Interrupt and transmission are not executed normally because write-pointer in FIFO
becomes abnormal condition. Therefore, manage number of writing by using software.
・ If transmit is sequential, writing the data to transmit FIFO every 16 bytes is always
needed. If writing other than 16 bytes, TEMP interrupt does not generate normally.
Note: If transmitting it by except 16 byte, use UNIT transmitting.
2) Receive
・ If read data with condition receive FIFO is empty, undefined data is read. Interrupt
and receiving are not executed normally because read-pointer in FIFO becomes
abnormal condition. Therefore, manage number of reading by using software.
・ If receive is sequential, reading the data from receive FIFO every 16 bytes is always
needed. If reading other than 16 bytes, RFUL interrupt does not generate normally.
Note: If transmitting it by except 16 byte, use UNIT receiving.
3) CRC
CRC is generated in I/O point. Please take care soft ware process to compare the CRC when used FIFO.
Ex. Sequential receive
1. Start sequential receive
2. finish valid data receive (FIFO_Full)
3. disable receive
4. valid data read from FIFO to temporary buffer(internal RAM)
5. CRC1 read from CRC generator in SPI circuit
6. CRC2 receive (enable UNIT receive from SD-CARD)
7. compare CRC1 and CRC2
Note: Above 2 to 4 process can be used DMAC, however it must stop sequential receive (process 3)
before to get CRC2 form SD-CARD.
92CZ26A-495
TMP92CZ26A