Table of Contents
Advertisement
TB0MOD
Bit symbol
(1182H)
Read/Write
After Reset
Prohibit
Function
Always write "0".
read-
modify-
write
TMRB0 source clock
Control clearing for up counter (UC10)
Capture/interrupt timing
Software capture
TMRB0 Mode Register
7
6
5
−
−
TB0CP0I
R/W
W*
0
0
1
Software
capture control
0: Execute
1: Undefined
00
01
<TB0CLK1:0>
10
11
0
<TB0CLE>
1
00
01
<TB0CPM1:0>
10
11
0
<TB0CP0I>
1
Figure 3.13.4 Register for TMRB (2)
92CZ26A-303
4
3
TB0CPM1 TB0CPM0
TB0CLE
R/W
0
0
Capture timing
Control
00:Disable
Up counter
INT6 occurs at
0:Disable
rising edge
1: Enable
01:TB0IN0 ↑
INT6 occurs at
rising edge
10: TB0IN0 ↑ TB0IN0 ↓
INT6 occurs at
falling edge
11: TA1OUT ↑
TA1OUT ↓
INT6 occurs at rising
edge
TB0IN0 pin input
φT1
φT4
φT16
Disable
Enable clearing by match with TB0RG1
Capture control
Disable
Capture to TB0CP0H/L at rising edge of TB0IN0
Capture to TB0CP0H/L at rising edge of TB0IN0
Capture to TB0CP1H/L at falling edge of TB0IN0
Capture to TB0CP0H/L at rising edge of TA1OUT
Capture to TB0CP1H/L at falling edge of TA1OUT
The value of up counter is captured to TB0CP0H/L
Undefined
TMP92CZ26A
2
1
0
TB0CLK1
TB0CLK0
0
0
0
TMRB0 source clock
00: TB0IN0 input
01: φT1
10: φT4
11: φT16
INT6 control
INT6 occurs at the rising
edge of TB0IN0
INT6 occurs at the rising
edge of TB0IN0
INT6 occurs at the rising
edge of TB0IN0
Advertisement
Table of Contents
