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Bit symbol
BC2
SBICR1
(1240H)
Read/Write
After Reset
Prohibit
Function
Number of transferred bits
Read-
(Note 1)
modify-
write
Note1: For the frequency of the SCL line clock, see 3.15.5 (3) Serial clock.
Note2: The initial data of SCK0 is "0", the initialdata of SWRMON is "1" if SBI operation is enable
(SBICR0<SBIEN>="1"). If SBI operation is disable (SBICR0<SBIEN>="0"), the initialdata of SWRMON is "0".
2
Note3: This I
C bus circuit does not support Fast-mode, it supports the Standard mode only. Although the I
circuit itself allows the setting of a baud rate over 100kbps, the compliance with the I
guaranteed in that case.
Serial Bus Interface Control Register 1
7
6
5
BC1
BC0
R/W
0
0
0
Figure 3.15.4 Registers for the I
92CZ26A-347
4
3
−
ACK
SCK2
R/W
R
0
1
Always
Internal serial clock selection and
Acknowledge
mode
read as
software reset monitor
specification
"1".
0: Not
generate
1: Generate
Internal serial clock selection <SCK2:0> at write
f
=80MHz (Output to SCL pin), Clock gear = fc/1
SYS
n = 4
−
000
n = 5
−
001
n = 6
−
010
n = 7
−
011
n = 8
100
68
n = 9
101
36
n = 10
110
18
111
(Reserved)
(Reserved)
Software reset state monitor <SWRMON> at read
0
During software reset
1
(Initial Data)
Acknowledge mode specification
0
Not generate clock pulse for acknowledge signal
1
Generate clock pulse for acknowledge signal
Number of bits transferred
<ACK> = 0
<BC2:0>
Number of
clock pulses
000
8
001
1
010
2
011
3
100
4
101
5
110
6
111
7
2
C bus mode
TMP92CZ26A
2
1
0
SCK0/
SCK1
SWRMON
R/W
R/W
0
0
0/1
(Note2)
System Clock: f
SYS
(=80MHz)
kHz
Clock Gear : fc/1
f
/4
SYS
fscl =
kHz
[Hz]
n
2
+ 35
kHz
<ACK> = 1
Bits
Number of
clock pulses
8
9
1
2
2
3
3
4
4
5
5
6
6
7
7
8
2
C specification is not
Bits
8
1
2
3
4
5
6
7
2
C bus
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