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3.16.3.15 FRAME Register
and is used for Isochronous transfer type.
FRAME_L
bit Symbol
(07E1H)
Read/Write
After reset
bit Symbol
FRAME_H
Read/Write
(07E2H)
After reset
T[10:7] (H register: Bit7 to bit4)
T[6:0] (L register: Bit6 to bit0)
CREATE (H register: Bit2)
0: DISABLE
1: ENABLE
FRAME STS[1:0]
(H register: Bit1 and bit0)
0: BEFORE
1: VALID
2: LOST
3.16.3.16 ADDRESS Register
enumeration.
bit Symbol
ADDRESS
(07E3H)
Read/Write
After reset
ADDRESS [6:0] (Bit6 to bit0)
This register shows frame number which is issued with SOF token from the host
Each HIGH and LOW registers show upper and lower bits.
7
6
−
T[6]
R
R
0
0
7
6
T[10]
T[9]
R
R
0
0
This register shows device address which is specified by the host in bus
By reading this register, a present address can be confirmed.
7
6
A6
R
0
ID, and UDC judges whether it is an effective transaction or
not.
5
4
T[5]
T[4]
T[3]
R
R
0
0
5
4
T[8]
T[7]
R
R
0
0
These bits are renewed when SOF-token is received.
And it shows frame-number.
These bits show enable function that generate SOF
SOF automatically from UDC. This is used for the case of
receiving error of SOF token.
This function is set by accessing COMMAND register.
By reset, this bit is initialized to "0".
These bits show the status whether a frame number
that is shown FRAME register is correct or not. At the
LOST status, a correct frame number is undefined.
If this register is "VALID", number that is shown to
FRAME register is correct.
If this register is "BEFORE", when SOF auto
generation, BEFORE condition shows it from USB host
controller inside that from SOF generation time to receive
SOF token. Correct value as frame-number is value that is
selected from FRAME register value.
5
4
A5
A4
A3
R
R
0
0
The UDC compares this register and address in all packet
This is initialized to "00H" by USB reset.
92CZ26A-397
TMP92CZ26A
3
2
1
T[2]
T[1]
R
R
R
0
0
0
3
2
1
CREATE
FRAME_STS1 FRAME_STS0
R
R
0
1
3
2
1
A2
A1
R
R
R
0
0
0
0
T[0]
R
0
0
R
0
0
A0
R
0
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