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PLLCR0
bit symbol
(10E8H)
Read/Write
After reset
Function
Note: Be carefull that logic of PLLCR0<LUPFG> is different from 900/L1's DFM.
PLLCR1
bit symbol
PLL0
(10E9H)
Read/Write
After reset
PLL0 for
CPU
0: Off
1: On
Function
bit symbol
Px7D
PxDR
(xxxxH)
Read/Write
After reset
Function
(Purpose and method of using)
• This register is used to set each pin-status at stand-by mode.
• All ports have this format's register. ("x" means port-name.)
• For each register, refer to 3.5 Function of Ports.
• Before "HALT" instruction is executed, set each register pin-status. They will be
effective after CPU executes "HALT" instruction.
• This register is effective in all stand-by modes (IDLE2, IDLE1 or STOP).
• This register is effective when using PMC function. For details, refer to PMC
section.
The truth table to control Output/Input-buffer is below.
Note1: OE means an output enable signal before stand-by mode. Basically, PxCR is used as OE.
Note2: "n" in PxnD means bit-number of PORTx.
7
6
5
FCSEL
LUPFG
R/W
R
0
0
Select
Lock-up
fc-clock
timer
0 : f
Status flag
OSCH
1 : f
0 : not end
PLL
1 : end
7
6
5
PLL1
LUPSEL
R/W
R/W
R/W
0
0
0
PLL1 for
Select
USB
stage of
0: Off
Lock up
1: On
counter
0: 12 stage
(for PLL0)
1:13 stage
(for PLL1)
Figure 3.3.5 SFR for PLL
7
6
5
Px6D
Px5D
1
1
1
Output/Input buffer drive-register for standby-mode
OE
PxnD
Output buffer
0
0
OFF
0
1
OFF
1
0
OFF
1
1
ON
Figure 3.3.6 SFR for drive register
92CZ26A-26
4
3
2
4
3
2
4
3
2
Px4D
Px3D
Px2D
R/W
1
1
1
Input buffer
OFF
ON
OFF
OFF
TMP92CZ26A
1
0
1
0
PLLTIMES
R/W
0
Select the
number of
PLL
0: ×12
1: ×16
1
0
Px1D
Px0D
1
1
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