Toshiba H1 Series Data Book page 506

Note 1: The value to be set in I2SnC<WSn5:0> must be 16 or larger (18 or larger for I2S transfer) when the data
length is 8 bits and 32 or larger (34 or larger for I2S transfer) when the data length is 16 bits.
Note 2: It is recommended that the value to be set in I2SnC<WSn5:0> be an even number. Although it is
possible to set an odd number, the clock duty of the WS signal does not become 50%. Setting an odd
number causes the High width of the WS signal to become longer by one I2SnCK0 pulse than the Low
width.
• Special function
As a special function available only in channel 0, the rising edge of the WS signal
can be used as an AD conversion start trigger for the AD converter in this LSI.
Setting I2S0CTL<SYSKE0>=1 and I2S0CTL<CNTE0>=1 enables the WS signal to
be sent to the AD converter. This can be done regardless of the setting of
I2S0CTL<TXE0>.
For details about AD conversion using the WS signal, refer to the chapter on the
AD converter.
(3) FIFO buffer and data format
The I S unit is provided with a 128-byte FIFO buffer (32-bit wide x 32-entry). The data
2
written to the 4 bytes (32 bits) of the I2SnBUF register is written to this FIFO buffer. This
FIFO must be written in units of 4 bytes. It is also necessary to consider the output order
and to distinguish between right data and left data.
To write data to the I2SnBUF register, be sure to use a 4-byte load instruction. If a
1-byte load instruction is used, invalid data will be transmitted. In case of using 1-byte or
2-byte transmission instruction, FIFO buffer isn't renewed and transmission isn't started.
And window addresses are 1800H (channel 0) and 1810H (channel1).
Write Data Size
1-byte access
2-byte access
4-byte access
Also note that data must be written in units of 64 bytes using the following sequence:
4-byte load instruction × 16 times = 64-byte data write
If data is not written in units of 64 bytes, interrupts cannot be generated at the normal
timing.
The I2SnCTL<TEMPn> flag is set to "1" when the FIFO buffer for each channel contains
no valid data. If there is even one byte of valid data in the FIFO, the flag is cleared to "0".
(The <TEMPn> flag is set to "1" as soon as the last valid data in the FIFO is sent to the
transmission shift register.)
Example instruction
ld (0x1800),a
ld (0x1800),wa
ld (0x1800),xwa
92CZ26A-503
8-bit width
Not allowed
Not allowed
OK
TMP92CZ26A
16-bit width
Not allowed
Not allowed
OK