Toshiba H1 Series Data Book page 52

(2) I/O register settings
Table 3.4.5 shows the I/O registers that are set by the boot program.
After the boot sequence, if execution moves to an application system program
without a reset being asserted, the settings of these I/O registers must be taken into
account. Also note that the registers in the CPU and the internal RAM remain in the
state after execution of the boot program.
Table 3.4.5 I/O Register Settings by Boot Program
Register Name Set Value
WDMOD 00H
WDCR B1H
SYSCR0 70H
SYSCR1 00H
SYSCR2 2CH
PLLCR0 00H
PLLCR1 00H
or
60H
INTEUSB 04H
INTETC01 44H
Note: The values to be set in the I/O registers for UART and USB are not described here. If these functions are
needed in a user program, set each I/O register as necessary.
Description
Watchdog timer not active
Watchdog timer disabled
High-frequency and low-frequency oscillators operating
Clock gear = 1/1
Initial value
PLL clock not used
Normally PLL is disabled.
However, only in the case of booting via USB, PLL is
activated for USB.
USB interrupt level setting
INTTC interrupt level setting
92CZ26A-49
TMP92CZ26A