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P7
bit Symbol
(001CH)
Read/Write
After reset
P7CR
bit Symbol
(001EH)
Read/Write
After reset
Function
bit Symbol
P7FC
Read/Write
(001FH)
After reset
Function
bit Symbol
P7DR
Read/Write
(0087H)
After reset
Function
P73 setting
<
<P73C>
0
<P73F>
0
Input Port
Output Port
Reserved
EA24Output
1
P76 setting
<P76C>
0
<P76F>
0
Input Port
Output Port
WAIT Input
1
Note1: Read-modify-write is prohibited for P7CR, P7FC.
Note2: When
and
NDRE
NDWE
Order
Registser bit2
------------------------------------------------------
(1)
P7
0
(2)
P7FC
1
(3)
P7CR
1
Note3: Note2: It is set to "Port" or "Data bus" by AM pins state.
7
6
5
P76
P75
Data from external port
(Output latch register is
set to "1")
Port 7 Control register
7
6
5
P76C
P75C
0
0
Port 7 Function register
7
6
5
P76F
P75F
0
0
0:Port
Refer to following table
1: WAIT
Port 7 Drive register
7
6
5
P76D
P75D
1
1
Input/Output buffer drive register for standby mode
P72 setting
<
<P72C>
1
<P72F>
0
Input Port
Reserved
1
P75 setting
<P75C>
1
<P75F>
0
Input Port
Reserved
NDR/
1
are used, set registers by following order to avoid outputting negative glitch.
bit1
0
1
1
Figure 3.7.11 Register for Port7
92CZ26A-127
Port 7 register
4
3
P74
P73
R/W
Data from external port
(Output latch register is
(Output latch register is
cleared to "0")
4
3
P74C
P73C
W
0
0
0: Input 1: Output
4
3
P74F
P73F
W
0
0
0:Port
1:
<P72>=0
WRLU
<P72>=1
4
3
P74D
P73D
R/W
1
1
P71 setting
<P71C>
0
1
<P71F>
Output Port
Output
NDWE
(at <P72>=0)
Output
WRLU
(at <P72>=1)
P74 setting
0
1
<P74F>
Output Port
Input
R/W Output
B
TMP92CZ26A
2
1
P72
P71
P70
Data from external port
set to "1")
2
1
P72C
P71C
0
0
2
1
P72F
P71F
P70F
0
0
0/1 Note3:
0:Port
0:Port
at
1:
1:
NDWE
RD
at
NDRE
at
<P71>=0
at
WRLL
<P71>=1
2
1
P72D
P71D
P70D
1
1
>
0
1
0
Input Port
Output Port
Reserved
Output
NDRE
(at <P71>=0)
1
Output
WRLL
(at <P71>=1)
<P74C>
0
1
0
Input Port
Output Port
Reserved
EA25Output
1
0
1
0
0
0
1
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