Toshiba H1 Series Data Book page 497

(6) SPIRD (SPI Receive Data Register)
SPIRD0, SPIRD1 registers are for reading received data.
SPIRD0
bit Symbol
RXD7
(834H)
Read/Write
After reset
Function
bit Symbol
RXD15
(835H)
Read/Write
After reset
Function
SPIRD1
bit Symbol
RXD7
(836H)
Read/Write
After reset
Function
bit Symbol
RXD15
(837H)
Read/Write
After reset
Function
This bit is for reading received data. When read, read it after confirming status of RFUL or
REND. The data is overwritten if write next data with transmit FIFO is not empty.
Receive register exist 4bytes. Therefore, it is possible reading by using 4byte instruction (use
DMA together it etc.)
However, when read data basically, read the data from 834 addresses. (There is exception)
Method of reading data (instruction) is restricted. Please refer to following table.
Receive
data
read size
1byte read
2 byte read
4 byte read
○: Read only valid data when CPU is reading.
△: Read valid data + invalid data when CPU is reading. Invalid data must be deleted after read.
×: Read only invalid data when CPU is reading.
*1: 834 address = valid data, 835 address = Invalid data,
*2: 834 address = valid data, 835 address = Invalid data, 836 address = Invalid data, 837 address = Invalid data
*3: 834 address = valid data, 835 address = valid data, 836 address = Invalid data, 837 address = Invalid data
SPIRD0 Register
7 6 5
RXD6 RXD5
0 0 0
15 14 13
RXD14 RXD13
0 0 0
SPIRD1 Register
7 6 5
RXD6 RXD5
0 0 0
15 14 13
RXD14 RXD13
0 0 0
Figure 3.17.13 SPIRD register
Instruction
example
1byte
receiving
<unit16>=0
○
ld a,(0x834)
×
ld a,(0x835)
△*1
ld wa,(0x834)
△*2
ld xwa,(0x834)
92CZ26A-494
4 3
RXD4 RXD3
R
0 0
Receive data register [7:0]
12 11
RXD12 RXD11
R
0 0
Receive data register [15:8]
4 3
RXD4 RXD3
R
0 0
Receive data register [7:0]
12 11
RXD12 RXD11
R
0 0
Receive data register [15:8]
UNIT receiving
(No using FIFO)
2 byte
receiving
<unit16>=1
○
○
○
△*3
TMP92CZ26A
2 1
RXD2 RXD1 RXD0
0 0
10 9
RXD10 RXD9 RXD8
0 0
2 1
RXD2 RXD1 RXD0
0 0
10 9
RXD10 RXD9 RXD8
0 0
Sequential receiving
(Using FIFO)
1 byte 2 byte
receiving receiving
<unit16>=0 <unit16>=1
Prohibit Prohibit
Prohibit Prohibit
○ ○
○ ○
0
0
8
0
0
0
8
0