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bit Symbol
LCDCTL0
(0285H)
Read/Write
After reset
PIP
function
0:Disable
1:Enable
Function
Note: When select STN mode, LCP0 is output at valid data only regardless of the setting of <LCP0OC> bit.
bit Symbol
LCDCTL1
Read/Write
(0286H)
After reset
LCP0
phase
Function
0: Rising
1: Falling
bit Symbol
LCDCTL2
Read/Write
(0287H)
After reset
LGOE2
phase
Function
0: Rising
1: Falling
bit Symbol
LCDDVM0
Read/Write
(0283H)
After reset
Function
bit Symbol
LCDDVM1
(0288H)
Read/Write
After reset
Function
LCD Control 0 Register
7
6
PIPE
ALL0
FRMON
R/W
R/W
R/W
0
0
Segment
FR divide
data
setting
0: Normal
0: Disable
1: Always
1: Enable
output "0"
LCD Control 1 Register
7
6
LCP0P
LHSP
LVSP
R/W
R/W
R/W
1
0
LHSYNC
LVSYNC
phase
phase
0: Rising
0: Rising
1: Falling
1: Falling
LCD Control 2 Register
7
6
LGOE2P
LGOE1P
LGOE0P
R/W
R/W
0
0
LGOE1
LGOE0
phase
phase
0: Rising
0: Rising
1: Falling
1: Falling
Divide FRM 0 Register
7
6
5
FMP3
FMP2
FMP1
0
0
0
LCP0 DVM (bits 3-0)
Divide FRM 1 Register
7
6
5
FMP7
FMP6
FMP5
0
0
0
LCP0 DVM (bits 7-4)
92CZ26A-511
5
4
3
–
R/W
0
0
Always
write "0"
5
4
3
LLDP
R/W
1
0
LLOAD
phase
0: Rising
1: Falling
5
4
3
R/W
0
4
3
FMP0
FML3
R/W
0
0
4
3
FMP4
FML7
R/W
0
0
TMP92CZ26A
2
1
DLS
LCP0OC
R/W
R/W
0
0
FR signal
LCP0(Note
LCDC
LCP0/Line
0: Always
operation
selection
output
1: At valid
0: Stop
0:Line
data only
1: Start
1:LCP0
LLOAD
width
0: At setting
in register
1: At valid
data only
2
1
LVSW1
R/W
0
LVSYNC
enable time control
00: 1 clock of LHSYNC
01: 2 clocks of LHSYNC
10: 3 clocks of LHSYNC
11: Reserved
2
1
2
1
FML2
FML1
FML0
0
0
LHSYNC DVM (bits 3-0)
2
1
FML6
FML5
FML4
0
0
LHSYNC DVM (bit 7-4)
0
START
R/W
0
0
LVSW0
R/W
0
0
0
0
0
0
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