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(6) LCD controller (1/6)
Symbol
Name
Address
LCD
LCD
mode0
0280H
MODE0
register
LCD
LCD
mode1
0281H
MODE1
register
LCD
divide
0283H
LCDDVM0
frame0
register
LCD
divide
0288H
LCDDVM1
frame1
register
LCD size
LCDSIZE
0284H
register
LCD
LCDCTL0
control0
0285H
register
7
6
5
RAMTYPE1 RAMTYPE0
SCPW1
0
0
LD bus transfer speed Mode setting
Display RAM
SCPW2= 0
00: 2-clock
00: Internal RAM
01: 4-clock
01: External SRAM
10: 8-clock
10: SDRAM
11: 16-clock
11: Reserved
SCPW2= 1
00: 6-clock
01: 12-clock
10: 24-clock
11: 48-clock
LDC2
LDC1
LDC0
0
0
Data rotation function
(Supported for 64K-color: 16bps only)
000: Normal
100: 90-degree
001: Horizontal flip
101: Reserved
010: Vertical flip
110: Reserved
111: Reserved
011: Horizontal & vertical flip
FMP3
FMP2
FMP1
0
0
0
LCP0 DVM (bits 3-0)
FMP7
FMP6
FMP5
0
0
0
LCP0 DVM (bits 7-4)
COM3
COM2
COM1
R/W
0
0
0
Common setting
0000 : reserved
1000 : 320
0001 : 64
1001 : 480
0010 : 96
1010 : Reserved
0011 : 120
1011 : Reserved
0100 : 128
1100 : Reserved
0101 : 160
1101 : Reserved
0110 : 200
1110 : Reserved
0111 : 240
1111 : Reserved
PIPE
ALL0
FRMON
R/W
0
0
PIP
Segment
FR divide
function
Data
setting
0:Disable
0:Normal
1:Enable
Always
1:
0: Disable
output "0"
1: Enable
92CZ26A-699
4
3
SCPW0
MODE3
R/W
1
1
0
0000 : Reserved
0001 : SR (mono)
0010 : SR (4Gray)
0011 : Reserved
0100 : SR (16Gray)
0101 : SR (64Gray)
0110 : STN (256 color)
0111 : STN
(4096 color)
LDINV
AUTOINV
R/W
0
0
0
LD bus
Auto bus
Inversion
inversion
0: Disable
1: enable
0: Normal
(Valid only
1: Inversion
for TFT)
FMP0
FML3
R/W
0
0
FMP4
FML7
R/W
0
0
COM0
SEG3
0
0
Segment setting
0000 : Reserved
0001 : 64
0010 : 128
0011 : 160
0100 : 240
0101 : 320
0110 : 480
0111 : 640
–
0
0
Always
write "0"
TMP92CZ26A
2
1
MODE2
MODE1
MODE0
0
0
1000 : Reserved
1001 : Reserved
1010 : TFT (256 color)
1011 : TFT (4096 color)
1100 : TFT (64k color)
1101 : TFT256k,16M
(color)
1110 : Reserved
1111 : Reserved
INTMODE
FREDGE
SCPW2
W
0
0
Interrupt
FR edge
LD bus
selection
transfer
0: LHSYNC
speed
front edge
0:LLOAD
1:LHSYNC
back edge
0: normal
1:LVSYNC
1: 1/3
FML2
FML1
FML0
0
0
LHSYNC DVM (bits 3-0)
FML6
FML5
FML4
0
0
LHSYNC DVM (bit 7-4)
SEG2
SEG1
SEG0
R/W
0
0
1000 : Reserved
1001 : Reserved
1010 : Reserved
1011 : Reserved
1100 : Reserved
1101 : Reserved
1110 : Reserved
1111 : Reserved
DLS
LCP0OC
START
R/W
0
0
LCDC
FR signal
LCP0
operation
LCP0/Line
0: Always
output
selection
1: At valid
0: Stop
0:Line
data only
1: Start
1:LCP0
LLOAD
width
0: At setting
in register
1: At valid
data only
0
0
W
0
0
0
0
0
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