Toshiba H1 Series Data Book page 382

32bit micro controller tlcs-900/h1 series
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3.16.3
UDC CORE
3.16.3.1 SFRs
The UDC CORE has following SFRs to control UDC and USB transceiver.
a)
FIFO
Endpoint 0 to 3 FIFO register
b)
Device request
bmRequestType
wValue_L
wIndex_L
wLength_L
c)
Status
Current_Config
StandardRequest
EPx_STATUS
d) Setup
EPx_BCS
Standard Request Mode
Descriptor RAM
e)
Control
EPx_MODE
COMMAND
Setup Received
f)
Others
ADDRESS
EPx_SIZE_L_A
EPx_SIZE_L_B
FRAME_L
USBBUFF TEST
register
register
register
register
register
register
register
register
register
register
register
register
register
register
register
register
register
register
92CZ26A-379
TMP92CZ26A
bRequest
register
wValue_H
register
wIndex_H
register
wLength_H
register
USB_STATE
register
Request
register
EPx_SINGLE
register
Request Mode
register
PortStatus
register
EOP
register
INT_ Control
register
USBREADY
register
DATASET
register
EPx_SIZE_H_A
register
EPx_SIZE_H_B
register
FRAME_H
register

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