Toshiba H1 Series Data Book page 93

3.6.2 SFRs
The DMAC has the following SFRs. These registers are connected to the CPU via a 16-bit
data bus.
(1) HDMASn (DMA Transfer Source Address Setting Register)
The HDMASn register is used to set the DMA transfer source address. When the source
address is updated by DMA execution, HDMASn is also updated.
HDMAS0 to HDMAS5 have the same configuration.
Although the bus sizing function is supported, the address alignment function is not
supported. Therefore, specify an even-numbered address for transferring 2 bytes and an
address that is an integral multiple of 4 for transferring 4 bytes.
bit Symbol DnSA7
HDMASn
Read/Write
After reset
Function
bit Symbol DnSA15
Read/Write
After reset
Function
bit Symbol DnSA23
Read/Write
After reset
Function
Channel 0
Channel 1
Channel 2
Channel 3
Channel 4
Channel 5
Note: Read-modify-write instructions can be used on all these registers.
HDMASn Register
7 6 5
DnSA6 DnSA5
0 0 0
15 14 13
DnSA14 DnSA13
0 0 0
23 22 21
DnSA22 DnSA21
0 0 0
Source address [23:16] for DMAn
Source address Source address
[23:16] [15:8]
(0902H) (0901H)
(0912H) (0911H)
(0922H) (0921H)
(0932H) (0931H)
(0942H) (0941H)
(0952H) (0951H)
Figure 3.6.2 HDMASn Register
92CZ26A-90
4 3
DnSA4 DnSA3
R/W
0 0
Source address [7:0] for DMAn
12 11
DnSA12 DnSA11
R/W
0 0
Source address [15:8] for DMAn
20 19
DnSA20 DnSA19
R/W
0 0
Source address
[7:0]
HDMAS0
(0900H)
HDMAS1
(0910H)
HDMAS2
(0920H)
HDMAS3
(0930H)
HDMAS4
(0940H)
HDMAS5
(0950H)
TMP92CZ26A
2 1 0
DnSA2 DnSA1 DnSA0
0 0 0
10 9 8
DnSA10 DnSA9 DnSA8
0 0 0
18 17 16
DnSA18 DnSA17 DnSA16
0 0 0