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bit Symbol
ADREG0L
(12A0H)
Read/Write
After reset
Function
bit Symbol
ADREG0H
(12A1H)
Read/Write
After reset
Function
bit Symbol
ADREG1L
(12A2H)
Read/Write
After reset
Function
bit Symbol
ADREG1H
(12A3H)
Read/Write
After reset
Function
Channel X conversion result
•
Bits 5 ∼ 2 are always read as "0".
•
Bit 0 is the AD conversion result store flag <ADRxRF>. When AD conversion result is stored, the flag is set to "1".
When Lower register (ADRECxL) is read, this bit is cleared to "0".
•
Bit 1 is the Overrun flag <OVRx>. This bit is set to "1" if a next conversion result is written to the ADREGxH/L
before both the ADREGxH and ADREGxL are read. This bit is cleared to "0" by reading Flag.
AD Conversion Result Register 0 Low
7
6
5
ADR01
ADR00
R
0
0
Store Lower 2 bits of
AN0 AD conversion
result
AD Conversion Result Register 0 High
7
6
5
ADR09
ADR08
ADR07
0
0
0
Store Upper 8 bits of AN0 AD conversion result
AD Conversion Result Register 1 Low
7
6
5
ADR11
ADR10
R
0
0
Store Lower 2 bits of
AN1 AD conversion
result
AD Conversion Result Register 1 High
7
6
5
ADR19
ADR18
ADR17
0
0
0
Store Upper 8 bits of AN1 AD conversion result
9
8
7
ADREGxH
7
6
5
4
Figure 3.23.6 AD Conversion Registers
92CZ26A-600
4
3
4
3
ADR06
ADR05
R
0
0
4
3
4
3
ADR16
ADR15
R
0
0
6
5
4
3
2
1
3
2
1
0
7
TMP92CZ26A
2
1
OVR0
ADR0RF
R
0
Overrun flag
AD conversion
result store
0:No generate
flag
1: Generate
1: Stored
2
1
ADR04
ADR03
ADR02
0
0
2
1
OVR1
ADR1RF
R
0
Overrun flag
AD conversion
result store
0:No generate
flag
1: Generate
1: Stored
2
1
ADR14
ADR13
ADR12
0
0
0
ADREGxL
6
5
4
3
2
1
0
0
R
0
0
0
0
R
0
0
0
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