Toshiba TMPM4K Series Reference Manual
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Toshiba TMPM4K Series Reference Manual

32-bit risc
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TMPM4K Group(1)
Product Inromation
32-bit RISC Microcontroller
TMPM4K Group(1)
Reference Manual
Product Information
(PINFO-M4K(1))
Revision 2.1
2018-09
1 / 89
2018-09-18
Rev. 2.1
© 2017-2018
Toshiba Electronic Devices & Storage Corporation

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  • Page 1 TMPM4K Group(1) Product Inromation 32-bit RISC Microcontroller TMPM4K Group(1) Reference Manual Product Information (PINFO-M4K(1)) Revision 2.1 2018-09 1 / 89 2018-09-18 Rev. 2.1 © 2017-2018 Toshiba Electronic Devices & Storage Corporation...

  • Page 2: Table Of Contents

    TMPM4K Group(1) Product Inromation Contents Preface ................................. 7 Related documents ..............................7 Conventions ................................8 Terms and Abbreviations ............................10 Overview ..............................11 Information of Peripheral Function ......................11 Register Base address ............................. 11 Trigger Selector(TRGSEL)..........................12 2.2.1. Trigger Selector List for the each Products ........................ 13 2.2.2.
  • Page 3 TMPM4K Group(1) Product Inromation 2.5.6. Internal signal connection specification ........................58 2.5.6.1. Trigger transfer signal connection ..........................58 2.5.6.2. T32A connection ................................59 Serial Peripheral Interface(TSPI) ........................60 2.6.1. Built-in channel ................................60 2.6.2. Function pin and port ..............................60 2.6.3.
  • Page 4 TMPM4K Group(1) Product Inromation Clock Selective Watchdog Timer(SIWDT) ..................... 77 2.13.1. Built-in channel ................................. 77 2.13.2. Count Clock ................................77 2.13.3. Output control ................................77 CRC calculation circuit(CRC) ........................78 RAM Parity(RAMP) ............................78 2.15.1. Built-in channel ................................. 78 2.15.2. Error detection block area ............................78 Oscillation Frequency Detection circuit(OFD)....................
  • Page 5 TMPM4K Group(1) Product Inromation List of Figures Figure 2.1 Example of Trigger Selector Connection ................12 List of Tables Table 2.1 Type of Register base address ....................11 Table 2.2 Trigger Selector List for each Product (1/5) ................13 Table 2.3 Trigger Selector List for each Product (2/5) ................14 Table 2.4 Trigger Selector List for each Product (3/5) ................
  • Page 6 TMPM4K Group(1) Product Inromation Table 2.52 PMD Inter-channel synchronous control connection ............. 72 Table 2.53 A-VE+ built-in channel ......................73 Table 2.54 A-VE+ Internal connection specification: Input ..............73 Table 2.55 A-VE+ Internal connection specification: Output ..............73 Table 2.56 A-ENC built-in channel ......................74 Table 2.57 A-ENC function pin .........................

  • Page 7: Preface

    TMPM4K Group(1) Product Inromation Preface Related documents Document name IP Symbol Input/Output Ports PORT-M4K(1) Exception EXCEPT-M4K(1) Clock Control and Operation Mode CG-M4K(1)-A Power supply and Reset operation RESET-M4K(1) DMA controller DMAC-B 32-bit Timer Event Counter T32A-B Asynchronous Serial Communication Circuit UART-C Serial Peripheral Interface TSPI-B...

  • Page 8: Conventions

    TMPM4K Group(1) Product Inromation Conventions Numeric formats follow the rules as shown below: Hexadecimal: 0xABC Decimal: 123 or 0d123 – Only when it needs to be explicitly shown that they are decimal numbers. Binary: 0b111 – It is possible to omit the "0b" when the number of bit can be distinctly understood from a sentence.
  • Page 9 TMPM4K Group(1) Product Inromation *********************************************************************************************************************** Arm, Cortex and Thumb are registered trademarks of Arm Limited (or its subsidiaries) in the US and/or elsewhere. All rights reserved. *********************************************************************************************************************** The Flash memory uses the Super Flash® technology under license from Silicon Storage Technology, Inc. Super Flash®...

  • Page 10: Terms And Abbreviations

    Oscillation Frequency Detector OPAMP Operational Amplifier RAMP RAM parity SIWDT Clock Selective Watchdog Timer TRGSEL Trigger Selection circuit Trimming circuit TSPI Toshiba Serial Peripheral Interface T32A 32-bit Timer Event Counter UART Universal Asynchronous Receiver Transmitter 10 / 89 2018-09-18 Rev. 2.1...

  • Page 11: Overview

    TMPM4K Group(1) Product Inromation Overview This chapter describes peripheral function-related channels or number of units, information of pins and product- specific function information. Use this chapter in conjunction with Reference Manual for Peripheral Function. Information of Peripheral Function Register Base address The following table shows the type of base address of each peripheral.

  • Page 12: Trigger Selector(Trgsel)

    TMPM4K Group(1) Product Inromation Trigger Selector(TRGSEL) The trigger selector is the circuit which chooses the one trigger and outputs the trigger signal to the peripheral function from two or more triggers inputted from the peripheral function, the port, etc. The trigger chosen from eight triggers by [TSEL0CRn]<INSELm> is outputted to the peripheral function of a connection destination.

  • Page 13: Trigger Selector List For The Each Products

    TMPM4K Group(1) Product Inromation 2.2.1. Trigger Selector List for the each Products Trigger selector of TMPM4K Group(1) consist of 11 control registers([TSEL0CR0 to 10]), and 41 triggers are controlled. The following table shows "Trigger Selector List of each Product". Table 2.2 Trigger Selector List for each Product (1/5) Product (:Available, -:N/A) Trigger Register...

  • Page 14: Table 2.3 Trigger Selector List For Each Product (2/5)

    TMPM4K Group(1) Product Inromation Table 2.3 Trigger Selector List for each Product (2/5) Product (:Available, -:N/A) Trigger Register Trigger Source source Bit Symbol M4K4 M4K2 M4K1 M4K0 T32A ch0 DMA request at capture B0 register T32A ch0 DMA request at capture B1 register T32A ch1 DMA request at capture B0 register INSEL8 DMA ch26...

  • Page 15: Table 2.4 Trigger Selector List For Each Product (3/5)

    TMPM4K Group(1) Product Inromation Table 2.4 Trigger Selector List for each Product (3/5) Product (:Available, -:N/A) Trigger Register Trigger Source source Bit Symbol M4K4 M4K2 M4K1 M4K0 PF0 (TRGIN0)  PB1 (TRGIN1)  PF2 (TRGIN2)  INSEL16 TSPI ch1 T32A ch5 Timer register A1 match trigger T32A ch5 Timer register B1 match trigger ...

  • Page 16: Table 2.5 Trigger Selector List For Each Product (4/5)

    TMPM4K Group(1) Product Inromation Table 2.5 Trigger Selector List for each Product (4/5) Product (:Available, -:N/A) Trigger Register Trigger Source source Bit Symbol M4K4 M4K2 M4K1 M4K0 T32A ch0 Timer register A0 match trigger T32A ch0 T32A ch0 Timer register A1 match trigger INSEL24 ...

  • Page 17: Table 2.6 Trigger Selector List For Each Product (5/5)

    TMPM4K Group(1) Product Inromation Table 2.6 Trigger Selector List for each Product (5/5) Product (:Available, -:N/A) Trigger Register Trigger Source source Bit Symbol M4K4 M4K2 M4K1 M4K0 PF0 (TRGIN0)    PB1 (TRGIN1)    PF2 (TRGIN2)  T32A ch3 UART ch3 transmission completion trigger INSEL32...

  • Page 18: Operation And Setting

    TMPM4K Group(1) Product Inromation 2.2.2. Operation and setting When using TRGSEL, please set an applicable clock enable bit to "1" (clock supply) in fsys supply stop register A ([CGFSYSENA], [CGFSYSMENA]), fsys supply stop register B ([CGFSYSENB], [CGFSYSMENB]), and fc supply stop registers ([CGFCEN]). An applicable register and the bit position vary according to a product.

  • Page 19: List Of Registers

    TMPM4K Group(1) Product Inromation 2.2.3. List of Registers The table below shows control registers and their addresses. Peripheral function Channel/Unit Base address Trigger selector TRGSEL 0x400BB800 Register name Address(Base+) Control Register 0 0x0000 [TSELxCR0] Control Register 1 0x0004 [TSELxCR1] Control Register 2 0x0008 [TSELxCR2] Control Register 3...

  • Page 20: Details Of Registers

    TMPM4K Group(1) Product Inromation 2.2.4. Details of Registers The following chapters show the detail of registers. The sign in the functional column parenthesis of each table expresses each function signal name. 2.2.4.1. [TSELxCR0] (Control Register 0) After Bit Symbol Type Function Reset Read as 0...
  • Page 21 TMPM4K Group(1) Product Inromation After Bit Symbol Type Function Reset Select the input trigger (DMA ch19) 000: T32A ch0 DMA request at match A1 register (T32A00DMAREQCMPA1) 001: T32A ch0 DMA request at match C1 register (T32A00DMAREQCMPC1) 010: T32A ch1 DMA request at match A1 register (T32A01DMAREQCMPA1) 14:12 INSEL1[2:0] 011: T32A ch1 DMA request at match C1 register (T32A01DMAREQCMPC1)

  • Page 22: Tselxcr1] (Control Register1)

    TMPM4K Group(1) Product Inromation 2.2.4.2. [TSELxCR1] (Control Register1) After Bit Symbol Type Function Reset Read as 0 Select the input trigger (DMA ch25) 000: T32A ch4 DMA request capture A0(T32A04DMAREQCAPA0) 001: T32A ch4 DMA request capture A1(T32A04DMAREQCAPA1) 010: T32A ch5 DMA request capture A0(T32A05DMAREQCAPA0) 30:28 INSEL7[2:0] 011: T32A ch5 DMA request capture A1(T32A05DMAREQCAPA1)
  • Page 23 TMPM4K Group(1) Product Inromation After Bit Symbol Type Function Reset Select the output trigger OUTSEL5 0: The edge detection is disable 1: The edge detection is enable Trigger output control 0: Disable 1: Enable Read as 0 Select the input trigger (DMA ch22) 000: T32A ch0 DMA request at match B1 register (T32A00DMAREQCMPB1) 001: T32A ch1 DMA request at match B1 register (T32A01DMAREQCMPB1) 010: T32A ch2 DMA request at match B1 register (T32A02DMAREQCMPB1)

  • Page 24: Tselxcr2] (Control Register 2)

    TMPM4K Group(1) Product Inromation 2.2.4.3. [TSELxCR2] (Control Register 2) After Bit Symbol Type Function Reset Read as 0 Select the input trigger (DMA ch29) 000: DMAC ch2 transfer completion(INTDMAATC2) 001: DMAC ch3 transfer completion(INTDMAATC3) 010: DMAC ch10 transfer completion(INTDMAATC10) 30:28 INSEL11[2:0] 011: DMAC ch11 transfer completion(INTDMAATC11) 100: DMAC ch18 transfer completion(INTDMAATC18) 101: DMAC ch19 transfer completion(INTDMAATC19)
  • Page 25 TMPM4K Group(1) Product Inromation After Bit Symbol Type Function Reset Select the output trigger OUTSEL9 0: The edge detection is disable 1: The edge detection is enable Trigger output control 0: Disable 1: Enable Read as 0 Select the input trigger (DMA ch26) 000: T32A ch0 DMA request capture B0(T32A00DMAREQCAPB0) 001: T32A ch0 DMA request capture B1(T32A00DMAREQCAPB1) 010: T32A ch1 DMA request capture B0(T32A01DMAREQCAPB0)

  • Page 26: Tselxcr3] (Control Register 3)

    TMPM4K Group(1) Product Inromation 2.2.4.4. [TSELxCR3] (Control Register 3) After Bit Symbol Type Function Reset Read as 0 Select the input trigger (TSPI ch0 trigger input) 000: PF0 (TRGIN0) 001: PB1 (TRGIN1) 010: PF2 (TRGIN2) 30:28 INSEL15[2:0] 011: T32A ch5 Timer register A1 match trigger(T32A05TRGOUTCMPA1) 100: T32A ch5 Timer register B1 match trigger (T32A05TRGOUTCMPB1) 101: T32A ch5 Timer register C1 match trigger (T32A05TRGOUTCMPC1) 110: Reserved...
  • Page 27 TMPM4K Group(1) Product Inromation After Bit Symbol Type Function Reset Select the output trigger OUTSEL13 0: The edge detection is disable 1: The edge detection is enable Trigger output control EN13 0: Disable 1: Enable Read as 0 Select the input trigger (DMA ch30) 000: DMAC ch4 transfer completion(INTDMAATC4) 001: DMAC ch5 transfer completion(INTDMAATC5) 010: DMAC ch12 transfer completion(INTDMAATC12)

  • Page 28: Tselxcr4] (Control Register 4)

    TMPM4K Group(1) Product Inromation 2.2.4.5. [TSELxCR4] (Control Register 4) After Bit Symbol Type Function Reset Read as 0 Select the input trigger (UART ch0 trigger input) 000: PF0 (TRGIN0) 001: PB1 (TRGIN1) 010: PF2 (TRGIN2) 30:28 INSEL19[2:0] 011: T32A ch5 Timer register A1 match trigger (T32A05TRGOUTCMPA1) 100: T32A ch5 Timer register B1 match trigger (T32A05TRGOUTCMPB1) 101: T32A ch5 Timer register C1 match trigger (T32A05TRGOUTCMPC1) 110: Reserved...
  • Page 29 TMPM4K Group(1) Product Inromation After Bit Symbol Type Function Reset Select the output trigger OUTSEL17 0: The edge detection is disable 1: The edge detection is enable Trigger output control EN17 0: Disable 1: Enable Read as 0 Select the input trigger (TSPI ch1 trigger input) 000: PF0 (TRGIN0) 001: PB1 (TRGIN1) 010: PF2 (TRGIN2)

  • Page 30: Tselxcr5] (Control Register 5)

    TMPM4K Group(1) Product Inromation 2.2.4.6. [TSELxCR5] (Control Register 5) After Bit Symbol Type Function Reset Read as 0 Select the input trigger (T32A ch0 Timer A internal trigger input) 000: PF0 (TRGIN0) 001: PB1 (TRGIN1) 010: PF2 (TRGIN2) 30:28 INSEL23[2:0] 011: UART ch0 transmission completion trigger (UART0TXTRG) 100: UART ch0 reception completion trigger (UART0RXTRG) 101: TSPI ch0 transmit completion (TSPI0TXEND)
  • Page 31 TMPM4K Group(1) Product Inromation After Bit Symbol Type Function Reset Select the output trigger OUTSEL21 0: The edge detection is disable 1: The edge detection is enable Trigger output control EN21 0: Disable 1: Enable Read as 0 Select the input trigger (UART ch1 trigger input) 000: PF0 (TRGIN0) 001: PB1 (TRGIN1) 010: PF2 (TRGIN2)

  • Page 32: Tselxcr6] (Control Register 6)

    TMPM4K Group(1) Product Inromation 2.2.4.7. [TSELxCR6] (Control Register 6) After Bit Symbol Type Function Reset Read as 0 Select the input trigger (T32A ch1 Timer B internal trigger input) 000: T32A ch1 Timer register A0 match trigger(T32A01TRGOUTCMPA0) 001: T32A ch1 Timer register A1 match trigger(T32A01TRGOUTCMPA1) 010: T32A ch1 Timer A overflow trigger(T32A01TRGOUTOFA) 30:28 INSEL27[2:0] 011: T32A ch1 Timer A underflow trigger(T32A01TRGOUTUFA)
  • Page 33 TMPM4K Group(1) Product Inromation After Bit Symbol Type Function Reset Select the output trigger OUTSEL25 0: The edge detection is disable 1: The edge detection is enable Trigger output control EN25 0: Disable 1: Enable Read as 0 Select the input trigger (T32A ch0 Timer B internal trigger input) 000: T32A ch0 Timer register A0 match trigger(T32A00TRGOUTCMPA0) 001: T32A ch0 Timer register A1 match trigger(T32A00TRGOUTCMPA1) 010: T32A ch0 Timer A overflow trigger(T32A00TRGOUTOFA)

  • Page 34: Tselxcr7] (Control Register 7)

    TMPM4K Group(1) Product Inromation 2.2.4.8. [TSELxCR7] (Control Register 7) After Bit Symbol Type Function Reset Read as 0 Select the input trigger (T32A ch2 Timer C internal trigger input) 000: T32A ch1 Timer register C0 match trigger(T32A01TRGOUTCMPC0) 001: T32A ch1 Timer register C1 match trigger(T32A01TRGOUTCMPC1) 010: T32A ch1 Timer C overflow trigger(T32A01TRGOUTOFC) 30:28 INSEL31[2:0] 011: T32A ch1 Timer C underflow trigger(T32A01TRGOUTUFC)
  • Page 35 TMPM4K Group(1) Product Inromation After Bit Symbol Type Function Reset Select the output trigger OUTSEL29 0: The edge detection is disable 1: The edge detection is enable Trigger output control EN29 0: Disable 1: Enable Read as 0 Select the input trigger (T32A ch1 Timer C internal trigger input) 000: T32A ch0 Timer register C0 match trigger (T32A00TRGOUTCMPC0) 001: T32A ch0 Timer register C1 match trigger (T32A00TRGOUTCMPC1) 010: T32A ch0 Timer C overflow trigger (T32A00TRGOUTOFC)

  • Page 36: Tselxcr8] (Control Register 8)

    TMPM4K Group(1) Product Inromation 2.2.4.9. [TSELxCR8] (Control Register 8) After Bit Symbol Type Function Reset Read as 0 Select the input trigger (T32A ch4 Timer A internal trigger input) 000: PF0 (TRGIN0) 001: PB1 (TRGIN1) 010: PF2 (TRGIN2) 30:28 INSEL35[2:0] 011: A-ENC ch0 divided pulse signal (ENC0TIMPLS) 100: Reserved 101: Reserved...
  • Page 37 TMPM4K Group(1) Product Inromation After Bit Symbol Type Function Reset Select the output trigger OUTSEL33 0: The edge detection is disable 1: The edge detection is enable Trigger output control EN33 0: Disable 1: Enable Read as 0 Select the input trigger (T32A ch3 Timer A internal trigger input) 000: PF0 (TRGIN0) 001: PB1 (TRGIN1) 010: PF2 (TRGIN2)

  • Page 38: Tselxcr9] (Control Register 9)

    TMPM4K Group(1) Product Inromation 2.2.4.10. [TSELxCR9] (Control Register 9) After Bit Symbol Type Function Reset Read as 0 Select the input trigger (T32A ch5 Timer B internal trigger input) 000: T32A ch5 Timer register A0 match trigger (T32A05TRGOUTCMPA0) 001: T32A ch5 Timer register A1 match trigger (T32A05TRGOUTCMPA1) 010: T32A ch5 Timer A overflow trigger (T32A05TRGOUTOFA) 30:28 INSEL39[2:0] 011: T32A ch5 Timer A underflow trigger (T32A05TRGOUTUFA)
  • Page 39 TMPM4K Group(1) Product Inromation After Bit Symbol Type Function Reset Select the output trigger OUTSEL37 0: The edge detection is disable 1: The edge detection is enable Trigger output control EN37 0: Disable 1: Enable Read as 0 Select the input trigger (T32A ch4 Timer B internal trigger input) 000: T32A ch4 Timer register A0 match trigger (T32A04TRGOUTCMPA0) 001: T32A ch4 Timer register A1 match trigger (T32A04TRGOUTCMPA1) 010: T32A ch4 Timer A overflow trigger (T32A04TRGOUTOFA)

  • Page 40: Tselxcr10] (Control Register 10)

    TMPM4K Group(1) Product Inromation 2.2.4.11. [TSELxCR10] (Control Register 10) After Bit Symbol Type Function Reset 31:7 Read as 0 Select the input trigger (T32A ch5 Timer C internal trigger input) 000: T32A ch4 Timer register C0 match trigger (T32A04TRGOUTCMPC0) 001: T32A ch4 Timer register C1 match trigger (T32A04TRGOUTCMPC1) 010: T32A ch4 Timer C overflow trigger (T32A04TRGOUTOFC) INSEL40[2:0] 011: T32A ch4 Timer C underflow trigger (T32A04TRGOUTUFC)

  • Page 41: Direct Memory Access Controller

    TMPM4K Group(1) Product Inromation Direct Memory Access Controller 2.3.1. Built-in unit Following table shows the built-in unit of each product. Table 2.7 DMAC built-in unit DMAC unit ( : Available, - : N/A ) Product Name Unit A M4K4  M4K2 ...

  • Page 42: Table 2.9 Dma Request Table (2/4)

    TMPM4K Group(1) Product Inromation Table 2.9 DMA request table (2/4) Single transfer Burst transfer ch No Trigger Signal name Signal name selector C ch0 transmission I2C0TXDMAREQ AD general purpose trigger ADATRG_DMAREQ [TSEL0CR0] AD single conversion ADASLG_DMAREQ <INSEL0> AD continue conversion ADACNT_DMAREQ T32A ch0 compare A1 matched T32A00DMAREQCMPA1...

  • Page 43: Table 2.10 Dma Request Table (3/4)

    TMPM4K Group(1) Product Inromation Table 2.10 DMA request table (3/4) Single transfer Burst transfer ch No Trigger Signal name Signal name selector T32A ch4 capture A0 T32A04DMAREQCAPA0 T32A ch4 capture A1 T32A04DMAREQCAPA1 T32A ch5 capture A0 T32A05DMAREQCAPA0 T32A ch5 capture A1 T32A05DMAREQCAPA1 [TSEL0CR1] <INSEL7>...

  • Page 44: Table 2.11 Dma Request List (4/4)

    TMPM4K Group(1) Product Inromation Table 2.11 DMA request list (4/4) Single transfer Burst transfer ch no. Signal name TRG selector Signal name DMAC ch4 transfer completion INTDMAATC4 DMAC ch5 transfer completion INTDMAATC5 DMAC ch12 transfer completion INTDMAATC12 DMAC ch13 transfer completion INTDMAATC13 [TSEL0CR3] <INSEL12>...

  • Page 45: 32-Bit Timer Event Counter(T32A)

    TMPM4K Group(1) Product Inromation 32-bit Timer Event Counter(T32A) 2.4.1. Built-in channel Following table shows the T32A built-in channel of each product. Table 2.12 T32A built-in channel T32A channel ( : Available, - : N/A ) Product M4K4    ...

  • Page 46: Functional Pins

    TMPM4K Group(1) Product Inromation 2.4.2. Functional pins The functional pins are assigned to the port of the following tables. Please do not use simultaneously the same function currently assigned to two or more pins. There is also a channel which does not have functional pins depending on a product. Table 2.13 T32A functional pin and port (1/2) Ports for products Functional pin...

  • Page 47: Table 2.14 T32A Functional Pins And Port (2/2)

    TMPM4K Group(1) Product Inromation Table 2.14 T32A functional pins and port (2/2) Ports for products Functional pin ( : Available, - : N/A ) Channel Port (Signal name) M4K4 M4K2 M4K1 M4K0 T32A03INA0 Input  T32A03INA1 Input  T32A03OUTA Output ...

  • Page 48: Clock For Prescaler

    TMPM4K Group(1) Product Inromation 2.4.3. Clock for prescaler The 32-bit timer event counter uses the clock of the following table as a prescaler clock. Table 2.15 T32A clock for prescaler Clock ΦT0 2.4.4. Internal signal connection specification 2.4.4.1. Capture trigger signal connection In the 32-bit timer event counter, capture trigger signal is connected to signals of the following table.

  • Page 49: Table 2.16 T32A Capture Trigger Connection (1/3)

    TMPM4K Group(1) Product Inromation Table 2.16 T32A Capture trigger connection (1/3) Channel Trigger source Input signal name of capture trigger Timer Trigger selector Input trigger signal Signal name T32A00TRGINAPHCK (Other timer output) PF0(TRGIN0) TRGIN0 PB1(TRGIN1) TRGIN1 PF2(TRGIN2) TRGIN2 Timer T32A00TRGINAPCK [TSEL0CR5] UART ch0 transmission completion trigger UART0TXTRG (Internal trigger input)

  • Page 50: Table 2.17 T32A Capture Trigger Connection (2/3)

    TMPM4K Group(1) Product Inromation Table 2.17 T32A Capture trigger connection (2/3) Channel Trigger source Input signal name of capture trigger Timer Trigger selector Input trigger signal Signal name T32A02TRGINAPHCK (Other timer output) PF0 (TRGIN0) TRGIN0 PB1 (TRGIN1) TRGIN1 PF2 (TRGIN2) TRGIN2 Timer T32A02TRGINAPCK...

  • Page 51: Table 2.18 T32A Capture Trigger Connection (3/3)

    TMPM4K Group(1) Product Inromation Table 2.18 T32A Capture trigger connection (3/3) Channel Trigger source Input signal name of capture trigger Timer Trigger selector Input trigger signal Signal name T32A04TRGINAPHCK (Other timer output) PF0 (TRGIN0) TRGIN0 Timer PB1 (TRGIN1) TRGIN1 T32A04TRGINAPCK [TSEL0CR8] (Internal trigger input) <INSEL35>...

  • Page 52: Synchronous Control Connection

    TMPM4K Group(1) Product Inromation 2.4.4.2. Synchronous control connection In the 32-bit timer event counter, as shown in the following tables, synchronous connection of the timer is carried out within the same channel. Table 2.19 T32A Synchronous control connection specifications Master Slave Channel Timer Timer...

  • Page 53: Pulse Counter List For Each Product

    TMPM4K Group(1) Product Inromation 2.4.5. Pulse Counter List for each product In the 32-bit timer event counter, as shown in the following tables, correspondence of a pulse counter changes with products. Table 2.20 T32A Pulse counter list for each product Channel M4K4 M4K2...

  • Page 54: Dma Request

    TMPM4K Group(1) Product Inromation 2.4.6. DMA request In the 32-bit timer event counter, DMA request are shown in the following table. What has the statement of a register name in the trigger selector column of a table should choose the request used by a trigger selector.

  • Page 55: Internal Signal Connection Specification

    TMPM4K Group(1) Product Inromation Table 2.22 T32A DMA request (2/2) DMA request channel Trigger Channel Request Signal name Single Burst selector transfer transfer DMA request at match A1 register T32A02DMAREQCMPA1 [TSEL0CR0]  <INSEL2> DMA request at match C1 register T32A02DMAREQCMPC1 [TSEL0CR1] DMA request at match B1 register T32A02DMAREQCMPB1...

  • Page 56: Universal Asynchronous Receiver Transmitter Circuit(Uart)

    TMPM4K Group(1) Product Inromation Universal Asynchronous Receiver Transmitter Circuit(UART) 2.5.1. Built-in channel Following table show the UART built-in channel of each product. In TMPM4K Group(1), Maximum Communication speed of UART is 5 Mbps. Table 2.23 UART built-in channel UART channel (: Available, - : N/A ) Product M4K4 ...

  • Page 57: Half Clock Mode Support

    TMPM4K Group(1) Product Inromation 2.5.3. Half Clock mode support Half clock mode of the UART corresponds to 1-pin mode only. 2.5.4. Clock for Prescaler The UART use the clock of the following table as a prescaler clock. Table 2.25 UART Clock for prescaler Clock ΦT0 2.5.5.

  • Page 58: Internal Signal Connection Specification

    TMPM4K Group(1) Product Inromation 2.5.6. Internal signal connection specification 2.5.6.1. Trigger transfer signal connection Transfer function of the UART has a trigger signal control. A trigger control signal is selected with the trigger source and use it as the following table. Table 2.27 UART trigger transfer signal connection Channel Trigger source...

  • Page 59: T32A Connection

    TMPM4K Group(1) Product Inromation 2.5.6.2. T32A connection In the UART, there is a signal connected with the peripheral function inside in addition to this as shown in the following table. Table 2.28 UART inside connection list: output Function output Output destination Trigger Channel Signal name...

  • Page 60: Serial Peripheral Interface(Tspi)

    TMPM4K Group(1) Product Inromation Serial Peripheral Interface(TSPI) 2.6.1. Built-in channel The following table shows the TSPI built-in channel of each product. In TMPM4K Group(1), Maximum Communication speed of TSPI is 20 Mbps. Table 2.29 TSPI built-in channel TSPI channel ( : Available, - : N/A ) Product M4K4 ...

  • Page 61: Transfer Mode Of Each Product

    TMPM4K Group(1) Product Inromation 2.6.3. Transfer mode of each product The transfer modes which can be used with the product as TSPI is shown in the following tables differ. Table 2.31 TSPI mode list Support Mode Channel M4K4 M4K2 M4K1 M4K0 SIO mode SIO mode...

  • Page 62: Internal Signal Connection Specification

    TMPM4K Group(1) Product Inromation 2.6.6. Internal signal connection specification 2.6.6.1. Trigger Transfer signal connection Transfer function of the TSPI has a trigger signal control. A trigger control signal is selected with the trigger source and use it as the following table. Table 2.34 TSPI trigger transfer Channel Trigger source...

  • Page 63: T32A Connection

    TMPM4K Group(1) Product Inromation 2.6.6.2. T32A connection In the TSPI, there is a signal connected with the peripheral function inside in addition to this as shown in the following table. Table 2.35 TSPI inside connection (output) Function output Output destination Trigger Channel Signal name...

  • Page 64: I 2 C Interface

    TMPM4K Group(1) Product Inromation C interface 2.7.1. Built-in channel The following table show the I C built-in channel of each product. The I C interface of TMPM4K Group(1) products supports "Standard Mode" and "Fast Mode". Table 2.37 I C interface built-in channel C channel ( : Available, - : N/A ) Product...

  • Page 65: Dma Request

    TMPM4K Group(1) Product Inromation 2.7.4. DMA request The following table shows the DMA request in the I "-" in the table does not have an applicable function. Table 2.40 I C interface DMA request DMA request channel Trigger Channel Request Signal name Single Burst...

  • Page 66: 12-Bit Analog To Digital Converter(Adc)

    TMPM4K Group(1) Product Inromation 12-bit Analog to Digital Converter(ADC) 2.8.1. Built-in unit The following table shows the ADC built-in unit of each product. Table 2.41 ADC built-in unit ADC unit ( : Available, - : N/A ) Product Unit A M4K4 ...

  • Page 67: Conversion Clock Of Adc

    TMPM4K Group(1) Product Inromation 2.8.3. Conversion clock of ADC The 12-bit ADC uses the clock of the following table as a conversion clock. Table 2.43 Conversion clock of ADC Clock ADCLK 2.8.4. Startup trigger The 12-bit ADC has an AD conversion function with the Trigger signal. The input trigger signal which has the register name in the trigger group selector column of the following table should choose the input trigger used by the trigger selector.

  • Page 68: Dma Request

    TMPM4K Group(1) Product Inromation 2.8.5. DMA request The following table shows the DMA request in the 12-bit ADC. Table 2.45 ADC DMA request DMA request channel Trigger Unit Request Signal name Single Burst selector transfer transfer General purpose trigger DMA request ADATRG_DMAREQ ...

  • Page 69: Advanced Programmable Motor Control Circuit(A-Pmd)

    TMPM4K Group(1) Product Inromation Advanced Programmable Motor Control Circuit(A-PMD) 2.9.1. Built-in channel The following table shows the A-PMD built-in channel of each product. Table 2.47 A-PMD built-in channel A-PMD channel ( : Available, - : N/A ) Product M4K4  ...

  • Page 70: Dma Request

    TMPM4K Group(1) Product Inromation 2.9.3. DMA request The following table shows the DMA request in the A-PMD. Table 2.49 A-PMD DMA request DMA request channel Trigger Channel Request Signal name Single Burst selector transfer transfer [TSEL0CR0] A-PMD ch0 PWM interrupt INTPWM0 ...

  • Page 71: Internal Signal Connection Specification

    TMPM4K Group(1) Product Inromation 2.9.4. Internal signal connection specification 2.9.4.1. Other connection In the A-PMD, there is a signal connected with the peripheral function inside in addition to this as shown in the following table. Table 2.50 A-PMD inside connection list: input Channel Function input Input source...

  • Page 72: Inter-Channel Synchronous Control Connection

    TMPM4K Group(1) Product Inromation Table 2.51 A-PMD inside connection list: output Output Channel Function output Signal name Signal name destination ADC synchronous trigger output 0 PMD0TRG0 PMD0TRG0 ADC synchronous trigger output 1 PMD0TRG1 PMD0TRG1 ADC synchronous trigger output 2 PMD0TRG2 PMD0TRG2 ADC synchronous trigger output 3 PMD0TRG3...

  • Page 73: Advanced Vector Engine Plus(A-Ve+)

    TMPM4K Group(1) Product Inromation Advanced Vector Engine Plus(A-VE+) 2.10.1. Built-in channel The following table shows the A-VE+ built-in channel of each product. Table 2.53 A-VE+ built-in channel A-VE+ channel ( : Available, - : N/A ) Product M4K4  M4K2 ...

  • Page 74: Advanced Encoder Input Circuit(A-Enc)

    TMPM4K Group(1) Product Inromation Advanced Encoder input circuit(A-ENC) 2.11.1. Built-in channel The following table shows the A-ENC built-in channel of each product. Table 2.56 A-ENC built-in channel A-ENC channel ( : Available, - : N/A ) Product M4K4  M4K2 ...

  • Page 75: Internal Signal Connection Specification

    TMPM4K Group(1) Product Inromation 2.11.3. Internal signal connection specification 2.11.3.1. T32A/A-PMD Connection In the A-ENC, there is a signal connected with the peripheral function inside in addition to this as shown in the following table. "-" in the table does not have an applicable function. Table 2.58 A-ENC Internal connection specification: Input Function Input Input source...

  • Page 76: Operational Amplifier (Opamp)

    TMPM4K Group(1) Product Inromation Operational amplifier (OPAMP) 2.12.1. Built-in unit The following table shows the OPAMP built-in unit of each product. Table 2.60 OPAMP built-in unitl OPAMP unit ( : Available, - : N/A ) Product M4K4    M4K2 ...

  • Page 77: Clock Selective Watchdog Timer(Siwdt)

    TMPM4K Group(1) Product Inromation Clock Selective Watchdog Timer(SIWDT) 2.13.1. Built-in channel The following table shows the SIWDT built-in channel of each product. Table 2.63 SIWDT built-in channel SIWDT channel Product (: Available, - : N/A) M4K4  M4K2  M4K1 ...

  • Page 78: Crc Calculation Circuit(Crc)

    TMPM4K Group(1) Product Inromation CRC calculation circuit(CRC) The following table shows the CRC built-in channel of each product. Table 2.66 CRC built-in channel CRC built-in Product (: Available, - : N/A) M4K4  M4K2  M4K1  M4K0  RAM Parity(RAMP) 2.15.1.

  • Page 79: Oscillation Frequency Detection Circuit(Ofd)

    TMPM4K Group(1) Product Inromation Oscillation Frequency Detection circuit(OFD) 2.16.1. Support products The OFD is supported by the following products. Table 2.69 OFD support product OFD support Product (: Available, - : N/A ) M4K4  M4K2  M4K1  M4K0 ...

  • Page 80: Debug Interface

    TMPM4K Group(1) Product Inromation Debug interface 2.17.1. Debug interface List for each product Table 2.72 Debug interface List support Pin list ( : Available, - : N/A ) Debug Pin Debug function Port (Signal name) M4K4 M4K2 M4K1 M4K0 SWDIO ...

  • Page 81: Non Break Debug Interface (Nbdif)

    TMPM4K Group(1) Product Inromation Non Break Debug Interface (NBDIF) 2.18.1. Correspondence table The following table shows the NBDIF correspondence of each product. Table 2.73 NBDIF correspondence table Function Product ( : Available, - : N/A ) M4K4  M4K2 M4K1 M4K0 2.18.2.

  • Page 82: Digital Noise Filter(Dnf)

    TMPM4K Group(1) Product Inromation Digital Noise Filter(DNF) 2.19.1. Built-in unit The following table shows the DNF built-in unit of each product. Table 2.75 DNF built-in unit DNF unit ( : Available, - : N/A ) Product M4K4  M4K2  M4K1 ...

  • Page 83: Sampling Source Clock

    TMPM4K Group(1) Product Inromation 2.19.3. Sampling source clock The clock which shows a digital noise filter circuit in the following tables as a sauce clock of a sampling is used. Table 2.77 DNF sampling source clock Clock Trimming Circuit(TRM) 2.20.1. Support products The TRM is supported by the following products.

  • Page 84: Voltage Detection Circuit(Lvd)

    TMPM4K Group(1) Product Inromation Voltage Detection Circuit(LVD) 2.21.1. Support products The LVD is supported by the following products. Table 2.80 LVD support product LVD support Product (: Available, - : N/A ) M4K4  M4K2  M4K1  M4K0  2.21.2.

  • Page 85: Flash Memory

    TMPM4K Group(1) Product Inromation Flash Memory 2.22.1. Clock for the Programming/Erasing As for flash memory, the clock of the following tables is used for programming/erasing of the code flash or the data flash. Table 2.82 Clock for Programming/Erasing Clock for Programming/Erasing IHOSC1 2.22.2.

  • Page 86: Single Boot Resource

    TMPM4K Group(1) Product Inromation 2.22.3. Single boot resource The peripheral function of the following table is used in single boot. Table 2.84 Single boot resource Peripheral function Channel Function Pin Name BOOT PJ6 (BOOT_N) PK0(UT0RXD) UART PK1(UT0TXDA) T32A 86 / 89 2018-09-18 Rev.

  • Page 87: Revision History

    TMPM4K Group(1) Product Inromation Revision History Table 3.1 Revision History Revision Date Description 2017-11-22 First release Revised (Revision No, Date, Copy Right) Revised Related documents table(added Exception & NBDIF, and IP Symbol) Revised Terms and Abbreviations(Op-Amp  OPAMP) Revised Table 2.5 (ch No of INSEL24) Revised Table 2.6 (ch No of INSEL40) Revised 2.2.4.3, 2.2.4.4 (INTDMAACTCx ...
  • Page 88 TMPM4K Group(1) Product Inromation - "2.4. 32-bit Timer Event Counter" Table 2.16, Table 2.17, Table 2.19: Added T32A to the title. Table 2.16 ch0/Timer A, ch1/Timer A: UART: completion  completion trigger TSPI: transmission transmit, reception receive ch0, 1/Timer B, C: compare matched triggermatch trigger Table 2.17 ch2/Timer A: UART: completion ...

  • Page 89: Restrictions On Product Use

    Before customers use the Product, create designs including the Product, or incorporate the Product into their own applications, customers must also refer to and comply with (a) the latest versions of all relevant TOSHIBA information, including without limitation, this document, the specifications, the data sheets and application notes for Product and the precautions and conditions set forth in the "TOSHIBA Semiconductor Reliability Handbook"...

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