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(15) 16-bit timer (2/2)
Symbol
Name
Address
TMRB1
TB1RUN
RUN
1190H
register
TMRB1
1192H
TB1MOD
MODE
(Prohibit
register
RMW)
TMRB1
1193H
Flip-Flop
TB1FFCR
(Prohibit
control
RMW)
register
16 bit timer
1198H
TB1RG0L
register 0
(Prohibit
low
RMW)
16 bit timer
1199H
TB1RG0H
register 0
(Prohibit
high
RMW)
119AH
16 bit timer
TB1RG1L
(Prohibit
register low
RMW)
16 bit timer
119BH
TB1RG1H
register 1
(Prohibit
high
RMW)
Capture
TB1CP0L
register 0
119CH
low
Capture
TB1CP0H
register 0
119DH
high
Capture
TB1CP1L
register 1
119EH
low
Capture
TB1CP1H
register 1
119FH
high
7
6
5
−
TB1RDE
R/W
R/W
0
0
Always
Double
write "0".
buffer
0: disable
1: enable
−
−
TB1CP0I TB1CPM1 TB1CPM0
R/W
W*
0
0
1
Always write "00".
Software
capture
control
0: Execute
1:
Undefined
−
−
TB1CT1
W *
1
1
0
Always write "11".
TB1FF0 inversion trigger
0: Disable trigger
* Always read as "11".
1: Enable trigger
When
capture
UC12 to
TB1CP1H/L
92CZ26A-735
4
3
I2TB1
TB1PRUN
R/W
R/W
0
TMRB0
IDLE2
prescaler
0: Stop
1: Operate
0: Stop and clear
1: Run (Count up)
TB1CLE
R/W
0
0
0
Control
Capture timing
Up
00: Disable
counter
INT7 occurs at rising
0:Clear
edge
Disable
01: TB1IN0 ↑
1:Clear
INT7 occurs at rising
Enable
edge
10: TB1IN0 ↑ TB1IN0 ↓
INT7 occurs at falling
edge
11: TA3OUT ↑
TA3OUT ↓
INT7 occurs at rising
edge
TB1C0T1 TB1E1T1 TB1E0T1 TB1FF0C1 TB1FF0C0
R/W
0
0
0
When
When UC12
When UC12
capture
matches
matches
UC12 to
with
with
TB0CP0H/L
TB1RG1H/L
TB1RG0H/L
−
W
0
−
W
0
−
W
0
−
W
0
−
R
Undefined
−
R
Undefined
−
R
Undefined
−
R
Undefined
TMP92CZ26A
2
1
0
TB1RUN
R/W
0
0
Up
counter
(UC12)
TB1CLK1 TB1CLK0
0
0
TMRB1 source clock
00: TB1IN0 input
01: φT1
10: φT4
11: φT16
W*
1
1
Control TB1FF0
00: Invert
01: Set
10: Clear
11: Don't care
* Always read as "11".
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