Table of Contents
Advertisement
3.16.3.25 EPx_SINGLE Register
EPx_SINGLE1
bit Symbol
(07D1H)
Read/Write
After reset
Note: Endpoint 3 support only SINGLE mode at TMP92CZ26A.
Bit number
0: No use
1: EP1_SINGLE
2: EP2_SINGLE
3: EP3_SINGLE
4: No use
5: EP1_SELECT
6: EP2_SELECT
7: EP3_SELECT
When EPx_SELECT bit is "1", EPx_SINGLE bit become valid in following content.
If set ting content of EPx_SINGLE bit to valid, set EPx_SELECT bit to "1".
3.16.3.26 EPx_BCS Register
EPx_BCS1
bit Symbol
(07D3H)
Read/Write
After reset
Bit number
0: No use
1: EP1_BCS
2: EP2_BCS
3: EP3_BCS
4: No use
5: EP1_SELECT
6: EP2_SELECT
7: EP3_SELECT
Always write "1" to EPx_BCS bit.
If setting content of EPx_BCS bit to valid, set EPx_SELECT bit to "1".
This register sets mode of FIFO in each endpoint (SINGLE/DUAL).
7
6
EP3_SELECT EP2_SELECT EP1_SELECT
R/W
R/W
0
0
0: DUAL mode
0: Invalid
This register set mode that access to FIFO in each endpoint.
7
6
EP3_SELECT EP2_SELECT EP1_SELECT
R/W
R/W
0
0
0: Reserved
0: Invalid
5
4
EP3_SINGLE EP2_SINGLE EP1_SINGLE
R/W
R/W
0
1: SINGLE mode
1: Valid
5
4
EP3_BCS
R/W
R/W
0
1: CPU access
1: Valid
92CZ26A-405
TMP92CZ26A
3
2
1
R/W
R/W
0
0
0
3
2
1
EP2_BCS
EP1_BCS
R/W
R/W
0
0
0
0
0
Advertisement
Table of Contents
