Toshiba H1 Series Data Book page 244

The and
NDRE
the NAND Flash are performed through the ND0FDTR register. The actual write operation
completes not when the ND0FDTR register is written to but when the data is written to the
external NAND Flash. Likewise, the actual read operation completes not when the
ND0FDTR register is read but when the data is read from the external NAND Flash.
At this time, the Low and High widths of
the CPU operating speed (f
the electrical characteristics.)
The following shows an example of accessing the NAND Flash in 6 clocks by setting
NDFMCR0<SPLW1:0>=2 and NDFMCR0<SPHW1:0>=2. (In write cycles, the data drive
time also becomes longer.)
Program Memory Read (1wait)
f
SYS
A23 ∼ A0
CS 2
RD
SRWR
NDCLE
NDALE
NDCE
NDRE
NDWE
NDR/B
D15 ∼ D0
Program Memory Read (1 wait)
f
SYS
A23 ∼ A0
CS 2
RD
SRWR
NDCLE
NDALE
NDCE
NDRE
NDWE
NDR/B
D15 ∼ D0
signals are explained next. Write and read operations to and from
NDWE
) and the access time of the NAND Flash. (For details, refer to
SYS
NAND Flash Read
FF1234H
IN (Program)
NAND Flash Write
FF1234H
IN (Program)
Figure 3.11.3 Read/Write Access to NAND Flash
92CZ26A-241
and can be adjusted according to
NDRE NDWE
001FF0H
2clk
2clk
IN (NAND Flash)
Program Memory Read (1 wait)
001FF0H
2clk
2clk
OUT (NAND Flash)
TMP92CZ26A
Program Memory Read (1 wait)
FF1238H
IN (Program)
FF1238H
IN (Program)