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bit Symbol
ADCCLK
(12BFH)
Read/Write
After reset
Function
Note1: AD conversion is executed at the clock frequency selected in the above register. To assure
conversion accuracy, however, the conversion clock frequency must not exceed 12MHz
MHz.
Note2: Don 't change the clock frequency while AD conversion is in progress.
f
SYS
(f
f
IO
40MHz
30MHz
AD conversion speed can be calculated by following.
Conversion speed = 120 × (1/ADCLK)
AD Conversion Clock Setting Register
7
6
5
Figure 3.23.11 AD Conversion Registers
÷1 ∼ ÷7
/2)
<ADCLK2:0>
SYS
100(f
/4)
IO
101(f
/5)
IO
011(f
/3)
IO
100(f
/4)
IO
92CZ26A-605
4
3
−
ADCLK2
R/W
R/W
0
Always
Select clock for AD conversion
write "0"
000 : Reserved
001 : f
010 : f
011 : f
<ADCLK2:0>
AD conversion
ADCLK
10.0MHZ
8MHZ
10.0MHZ
7.5MHZ
TMP92CZ26A
2
1
0
ADCLK1
ADCLK0
R/W
R/W
0
0
0
100 : f
/4
IO
/1
101 : f
/5
IO
IO
/2
110 : f
/6
IO
IO
/3
111 : f
/7
IO
IO
ADCLK
speed
12 μsec
15 μsec
12 μsec
16 μsec
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