Toshiba H1 Series Data Book page 31

3.3.4 Clock doubler (PLL)
PLL0 outputs the f
low-speed frequency oscillator can be used as external oscillator, even though the internal
clock is high-frequency.
Since Reset initializes PLL0 to stop status, setting to PLLCR0 and PLLCR1-register is
needed before use.
Like an oscillator, this circuit requires time to stabilize. This is called the lock-up time
and it is measured by 12-stage binary counter. Lock-up time is about 0.41ms at f
10MHz.
PLL (PLL1) which is special for USB is build in. Lock-up time is about 0.82ms at f
10MHz measured by 13-stage binary counter.
Note1: Input frequency limitation for PLL
The limitation of input frequency (High frequency oscillation) for PLL is following.
f = X to X MHz (Vcc = 1.4 to 1.6V)
OSCH
Note2: PLLCR0<LUPFG>
The logic of PLLCR0<LUPFG> is different from 900/L1's DFM.
Be careful to judge an end of lock-up time.
Note3: PLLCR1<PLL0>, PLLCR1<PLL1>
It's prohibited to turn ON both PLL0 and PLL1 simultaneously.
If turning ON simultaneously, one PLL should be turn ON after finishing the lock up of the other PLL.
Figure 3.3.7 shows the frequency of f
=10MHz.
f
OSH
10MHz
clock signal, which is 12 or 16 times as fast as f
PLL
f
PLL
fc
f 10MHz 10MHz
OSH
× 12 120MHz
60MHz
× 16 160MHz
80MHz
Figure 3.3.7 The frequency of f
92CZ26A-28
when using PLL and clock gear at f
SYS
Frequency of f
SYS
fc/2 fc/4
5MHz 2.5MHz 1.25MHz
30MHz 15MHz
40MHz 20MHz
at f =10MHz
SYS OSH
TMP92CZ26A
. That is, the
OSCH
OSCH
OSCH
fc/8 fc/16
625KHz
7.5MHz 3.75MHz
10MHz 5MHz
=
=
OSCH