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3.3.6
Standby controller
(1) Halt Modes and Port Drive-register
When the HALT instruction is executed, the operating mode switches to IDLE2,
IDLE1 or STOP Mode, depending on the contents of the SYSCR2<HALTM1 to 0>
register and each pin-status is set according to PxDR-register.
bit symbol
Px7D
PxDR
(xxxxH)
Read/Write
After reset
Function
(Purpose and method of using)
• This register is used to set each pin-status at stand-by mode.
• All ports have this format's register. ("x" means port-name.)
• For each register, refer to 3.5 Function of Ports.
• Before "HALT" instruction is executed, set each register pin-status. They will be
effective after CPU executes "HALT" instruction.
• This register is effective in all stand-by modes (IDLE2, IDLE1 or STOP).
• This register is effective when using PMC function. For details, refer to PMC
section.
The truth table to control Output/Input-buffer is below.
Note1: OE means an output enable signal before stand-by mode.Basically, PxCR is used as OE.
Note2: "n" in PxnD means bit-number of PORTx.
The subsequent actions performed in each mode are as follows:
7
6
5
Px6D
Px5D
1
1
1
Output/Input buffer drive-register for standby-mode
OE
PxnD
Output buffer
0
0
OFF
0
1
OFF
1
0
OFF
1
1
ON
a. IDLE2: Only the CPU halts.
The internal I/O is available to select operation during IDLE2 mode by
setting the following register.
Table 3.3.2 shows the registers of setting operation during IDLE2 mode.
Table 3.3.2 SFR setting operation during IDLE2 mode
Internal I/O
TMRA01
TMRA23
TMRA45
TMRA67
TMRB0
TMRB1
SIO0
SBI
A/D converter
WDT
b. IDLE1: Only the oscillator, RTC (real-time clock), and MLD continue to
operate.
c. STOP: All internal circuits stop operating.
92CZ26A-34
4
3
2
Px4D
Px3D
Px2D
R/W
1
1
1
Input buffer
OFF
ON
OFF
OFF
SFR
TA01RUN<I2TA01>
TA23RUN<I2TA23>
TA45RUN<I2TA45>
TA67RUN<I2TA67>
TB0RUN<I2TB0>
TB1RUN<I2TB1>
SC0MOD1<I2S0>
SBIBR0<I2SBI>
ADMOD1<I2AD>
WDMOD<I2WDT>
TMP92CZ26A
1
0
Px1D
Px0D
1
1
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