Toshiba H1 Series Data Book page 197

RDTMGCR0/1<BnTCRS1:0>
00
01
10
11
TCRS:The delay from (CSn) to (RD,SRxxB).
SDCLK
(80MHz)
A23 to 0
CSn
R/
W
RD
Read
SRxxB
cycle
D15 to 0
WRxx
Write
SRWR
cycle
SRxxB
D15 to 0
Note: TW cycle is inserted by setting BnCSL register. If it is set to 0-Wait, TW cycle is not inserted.
TCRS = 0.5 × f
SYS
TCRS = 1.5 × f
SYS
TCRS = 2.5 × f
SYS
TCRS = 3.5 × f
SYS
T2
T1
TAC
TCRS
TCWS
TCWS
92CZ26A-194
(Default)
TW
T3 Tn-2
Output
TMP92CZ26A
Tn-1 Tn
TAC
TCRH
Input
TCWH
Output