Toshiba H1 Series Data Book page 351

SBICR2 Bit symbol MST
(1243H)
Read/Write
After reset
Prohibit
Function Master/Slave
Read-
selection
modify-
0:Slave
write
1:Master
Note 1: Reading this register functions as SBISR register.
Note 2: Switch a mode to port mode after confirming that the bus is free.
Switch a mode between I
high-level.
Serial Bus Interface Control Register 1
7 6 5
TRX BB
W
0 0 0
Transmitter Start/Stop
/Receiver condition
selection Generation
0:Generate
0:Receiver
stop
1:Transmitter
condition
1:Generate
start
condition
2
C bus mode and port mode after confirming that input signals via port are
Figure 3.15.5 Registers for the I
Table 3.15.1Resolution of base clock
Clock Gear
<GEAR1:0>
000(fc)
001(fc/2)
010(fc/4)
011(fc/8)
100(fc/16)
92CZ26A-348
4 3
PIN SBIM1
W (Note 1)
1 0
Cancel Serial bus interface
INTSBI operating mode selection
interrupt (Note 2)
request 00: Port mode
0:Don't care 01: (Reserved)
2
1:Cancel 10: I C Bus mode
interrupt 11: (Reserved)
request
Serial bus interface operating mode selection (Note2)
00 Port Mode (Serial Bus Interface output disabled)
01 Reserved
2
10 I C Bus Mode
11 Reserved
2
C bus mode
@f = 80MHz
SYS
Base Clock
Resolution
2
f /2 (50ns)
SYS
3
f /2 (0.1us)
SYS
4
f /2 (0.2us)
SYS
5
f /2 (0.4us)
SYS
6
f /2 (0.8us)
SYS
TMP92CZ26A
2 1
SBIM0 SWRST1 SWRST0
W (Note 1)
0 0
Software reset generate
write "10" and "01", then
an internal reset signal is
generated.
0
0