Toshiba H1 Series Data Book page 500

3.18.1 Block Diagram
The I S unit contains two channels: channel 0 and channel 1. Each channel can be controlled
2
and made to output independently.
Figure 3.18.1 shows a block diagram for I
I2S0CTL
<CLKS0>
f
SYS
f
I2S
<CK07:00>
0 1
32bit
64-byte FIFO0
(2 bytes×32)
8-bit
Counter
I2S0C
6-bit
Counter
I2S0C
<WS05:00>
Clock Generator
31 0 1 31
64-byte FIFO1
(2 bytes×32)
FIFO Control
Write Pointer
Read Pointer
Figure 3.18.1 I
92CZ26A-497
S channel 0.
2
I2SCKO
Control
I2S0CTL
<EDGE0,TXE0,I2SCLKE0>
I2SWS
Control
I2S0CTL
<DTFMT01:00,
WLVL0>
Data Selector
Interrupt
Control
I2S0CTL
<DTFMT01:00>
<DIR0>
<BIT0>
Request Signal Output to ADC
(Supported in channel 0 only)
2
S Block Diagram
TMP92CZ26A
I2S0CKO
I2S0WS
INTI2S0
I2S0CTL
<DIR0>
I2S0DO