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bit Symbol
ADREG2L
(12A4H)
Read/Write
After reset
Function
bit Symbol
ADREG2H
(12A5H)
Read/Write
After reset
Function
bit Symbol
ADREG3L
(12A6H)
Read/Write
After reset
Function
bit Symbol
ADREG3H
(12A7H)
Read/Write
After reset
Function
Channel X conversion result
•
Bits 5 ∼ 2 are always read as "0".
•
Bit 0 is the AD conversion result store flag <ADRxRF>. When AD conversion result is stored, the flag is set to "1".
When Lower register (ADRECxL) is read, this bit is cleared to "0".
•
Bit 1 is the Overrun flag <OVRx>. This bit is set to "1" if a next conversion result is written to the ADREGxH/L
before both the ADREGxH and ADREGxL are read. This bit is cleared to "0" by reading Flag.
AD Conversion Result Register 2 Low
7
6
5
ADR21
ADR20
R
0
0
Store Lower 2 bits of
AN2 AD conversion
result
AD Conversion Result Register 1 High
7
6
5
ADR29
ADR28
ADR27
0
0
0
Store Upper 8 bits of AN2 AD conversion result
AD Conversion Result Register 3 Low
7
6
5
ADR31
ADR30
R
0
0
Store Lower 2 bits of
AN3 AD conversion
result
AD Conversion Result Register 3 High
7
6
5
ADR39
ADR38
ADR37
0
0
0
Store Upper 8 bits of AN3 AD conversion result
9
8
7
6
ADREGxH
7
6
5
4
Figure 3.23.7 AD Conversion Registers
92CZ26A-601
4
3
4
3
ADR26
ADR25
R
0
0
4
3
4
3
ADR36
ADR35
R
0
0
5
4
3
2
1
0
3
2
1
0
7
6
TMP92CZ26A
2
1
0
OVR2
ADR2RF
R
R
0
0
Overrun flag
AD conversion
result store
0:No generate
flag
1: Generate
1: Stored
2
1
0
ADR24
ADR23
ADR22
0
0
0
2
1
0
OVR3
ADR3RF
R
R
0
0
Overrun flag
AD conversion
result store
0:No generate
flag
1: Generate
1: Stored
2
1
0
ADR34
ADR33
ADR32
0
0
0
ADREGxL
5
4
3
2
1
0
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