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3.19.3.5
Refresh Rate
The period of the horizontal synchronization signal LHSYNC is defined as the
product of the value set in LCDHSP<LH15:0> and the LCP0 clock period.
The value to be set in LCDHSP<LH15:0> is obtained as follows:
TFT
Segment size + number of dummy clocks
STN
Monochrome/grayscale : (Segment size / 8) + number of dummy clocks
Color
LHSYNC [s: period] = LCP0 [s: period] × (<LH15:0> + 1)
bit Symbol
LCDHSP
Read/Write
(028AH)
After reset
Function
(028BH)
bit Symbol
Read/Write
After reset
Function
The period of the vertical synchronization signal LVSYNC is defined as the product of
the value set in LCDVSP<LV9:0> and the LHSYNC period.
The value to be set in LCDVSP<LV9:0> is obtained as follows:
TFT
Common size + number of dummy clocks
STN
Common size + number of dummy clocks
porch.)
LVSYNC [s: period] = LHSYNC [s: period] × (<LV9:0> + 1)
bit Symbol
LCDVSP
Read/Write
(028CH)
After reset
Function
(028DH)
bit Symbol
Read/Write
After reset
Function
: (Segment size × 3 / 8) + number of dummy clocks
LCD LHSYNC Pulse Register
7
6
5
LH7
LH6
LH5
0
0
0
7
6
5
LH15
LH14
LH13
0
0
0
(A minimum of one dummy clock must be inserted in the back
= LCP0 [s: period] × (<LH15:0> + 1) × (<LV9:0> + 1)
LCD V SYNC Pulse Register
7
6
5
LVP7
LVP6
LVP5
0
0
0
7
6
5
92CZ26A-523
(*)
4
3
LH4
LH3
W
0
0
LHSYNC period (bits 7–0)
4
3
LH12
LH11
W
0
0
LHSYNC period (bits 15-8)
(*)
(*)
4
3
LVP4
LVP3
W
0
0
LVSYNC period (bits 7-0)
4
3
LVSYNC period (bits 9-8)
TMP92CZ26A
(*)
(*)
2
1
0
LH2
LH1
LH0
0
0
0
2
1
0
LH10
LH9
LH8
0
0
0
2
1
0
LVP2
LVP1
LVP0
0
0
0
2
1
0
LVP9
LVP8
W
0
0
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