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3.10.2 Operation Description
(1) Memory access control
The SDRAMC is enabled by setting SDACR<SMAC> to "1".
When one of the bus masters (CPU, LCDC, DMAC) generates a cycle to access the SDRAM
address area, the SDRAMC outputs SDRAM control signals.
Figure3.10.2 to Figure3.10.5 shows the timing for accessing the SDRAM. The number of
SDRAM access cycles is controlled by the SDRAMC and does not depend on the number of
waits controlled by the memory controller.
(a)
Command issue function
The SDRAMC issues commands as specified by the SDCMM register. The SDRAMC also
issues commands automatically for each SDRAM access cycle generated by each bus
master.
Table 3.10.1 shows the commands that are issued by the SDRAMC.
Command
Bank Activate
Precharge All
Read
Read with Auto Precharge
Write
Write with Auto Precharge
Mode Register Set
Burst Stop
Auto Refresh
Self Refresh Entry
Self Refresh Exit
Note 1: H = High level, L = Low level, RA = Row address, CA = Column address, M = Mode data, X = Don't care
Note 2: CKE
= CKE level in the command input cycle
n
CKE
= CKE level in a cycle immediately before the command input cycle
n-1
Table 3.10.1 Commands Issued by the SDRAMC
CKE
CKE
SDxxDQM
n-1
n
H
H
H
H
H
H
H
H
L
H
H
L
H
H
L
H
H
L
H
H
H
H
H
H
H
H
H
H
L
H
L
H
H
92CZ26A-223
A15-11
A10
SDCS
SDRAS SDCAS SDWE
A9-0
RA
RA
L
H
X
L
L
CA
L
H
CA
L
L
CA
L
H
CA
L
L
M
L
X
X
L
X
X
L
X
X
L
X
X
H
TMP92CZ26A
L
H
H
L
H
L
H
L
H
H
L
H
H
L
L
H
L
L
L
L
L
H
H
L
L
L
H
L
L
H
H
H
H
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