Toshiba H1 Series Data Book page 447

32bit micro controller tlcs-900/h1 series
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Wait transmission event
DATASET = 0
DATASET = 1
Wait transmitting
rest data
If transmitting finish normally,
it clears applicable bit of DATASET.
Figure 3.16.16 Transmitting Sequence in Single Packet Mode
Below is transmitting sequence in single packet mode.
DATASET register
• Check bit of EPx_DSET_A
Transmitting number > payload
• WR of payload to applicable endpoint
• Total = Total − payload
If transmitting number reach to
payload, applicable bit of
DATASET register is set 1
Wait IN token
92CZ26A-444
IDLE
Transmission event
Distinction
transmitting
Transmitting number < payload
• WR of transmitting number applicable endpoint
• Total = 0
EOP register
WR 0 to only bit of applicable endpoint
Wait transmitting
• Must access to EOP register in transmitting
• This is used showing to the closing control
Finish
transmitting
TMP92CZ26A
short packet.
transfer type.
If you access to endpoint 0, you must to
access in closing control transfer type.

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