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PV
bit Symbol
PV7
(00A8H)
Read/Write
Data from external port
After reset
(Output latch register is
PVCR
bit Symbol
PV7C
(00AAH)
Read/Write
After reset
Function
0: Input 1: Output
bit Symbol
PV7F
PVFC
(00ABH)
Read/Write
After reset
Function
Refer to following table
PV2 setting
<PV2C>
0
<PV2F>
Input port
Output port
0
Reserved
1
bit Symbol
PV7F2
PVFC2
Read/Write
(00A9H)
After reset
0:CMOS
Function
1:Open
PVDR
bit Symbol
PV7D
(009DH)
Read/Write
After reset
Function
Note: Read-Modify-Write is prohibited for the registers PVCR, PVFC and PVFC2.
7
6
5
PV6
R/W
cleared to "0")
Port V control register
7
6
5
PV6C
0
0
Port V function register
7
6
5
PV6F
W
0
0
PV1 setting
<PV1C>
1
<PV1F>
Input port
0
Reserved
Reserved
1
PV7 setting
<PV7C>
<PV7F>
Input port
0
Reserved
1
Port V function register 2
7
6
5
PV6F2
W
W
0
0
0:CMOS
1:Open
-drain
-drain
Port V drive register
7
6
5
PV6D
R/W
1
1
Input/Output buffer drive register for standby mode
Figure 3.7.60 Register for Port V
92CZ26A-171
Port V register
4
3
PV4
PV3
Data from external port
(Output latch register is cleared to "0")
4
3
4
3
0
1
Output port
Reserved
0
1
Output port
SCL I/O
4
3
4
3
PV4D
PV3D
1
1
TMP92CZ26A
2
1
0
PV2
PV1
PV0
R/W
2
1
0
PV2C
PV1C
PV0C
W
0
0
0
0: Input 1: Output
2
1
0
PV2F
PV1F
PV0F
W
0
0
0
Refer to following table
PV0 setting
<PV0C>
0
<PV0F>
Input port
Output port
0
Reserved
1
SCLK0 output
Note: SCLK0 is only output.
PV6 setting
<PV6C>
0
<PV6F>
Input port
Output port
0
Reserved
1
SDA I/O
2
1
0
2
1
0
PV2D
PV1D
PV0D
R/W
1
1
1
1
1
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